Piclist:
Is there a Min and a Max voltage for a 12C672 port pin that is used as an
analog input? I understand that going past Vdd or Vss will cause accuracy
problems, but if it is powered with +5V, will 10V at the input cause a
problem? Will the protection diode get burnt? Or will I need to ensure that
voltages presented to the input stay within a certain range?
This is a general problem: the start-up of the power supplies with signals
already applied to the chips. I have not yet a final solution, and would
like to read other opinions.
If you read the Ratings you will find (i have not here the data) about 5,5V
and if Vin > Vcc, to protect the input clamping circuit, you must limit the
current to < 20mA.
If you use a resistor in series to limit the current to a few mA, in each
input, I think ( not 100% sure ) you have protected the device. Of course R
+ parasitic C is a filter and you are limiting the high frequency response.
My .2 cent.
Regards
Fernando
Fernando wrote:
>Hi Bill,
>
>This is a general problem: the start-up of the power supplies with signals
>already applied to the chips. I have not yet a final solution, and would
>like to read other opinions.
Yes, this is a problem. The pullup clamping diodes on the PIC I/O pins
provide a sneak pathway for external signals to get onto the Vdd line,
and the PIC will be powered or partially powered. Then, when you turn
on the Vdd supply proper, the chip may not reset correctly. I try not
to do this, but others may have a hard solution. Adding a series R in
I/O will help, but may not solve this problem. A properly-designed
reset ckt may help here.
===============
>If you read the Ratings you will find (i have not here the data) about 5,5V
>and if Vin > Vcc, to protect the input clamping circuit, you must limit the
>current to < 20mA.
>If you use a resistor in series to limit the current to a few mA, in each
>input, I think ( not 100% sure ) you have protected the device. Of course R
>+ parasitic C is a filter and you are limiting the high frequency response.
I don't believe the RC due to parasitic C will matter very much, given
the frequency range of signals "normally" applied to a PIC. Assuming Cpara
of about 20 pF [high-estimate], and R = 3.3K, F3db = 1/(2*pi*R*C) = 2.4 Mhz.
Series R of 3.3K will protect the PIC to overvoltages in the range of
20 mA * 3.3K = 66V. However, it can also supply ~1.5 mA via the sneak
pathway described above.
Going with a much larger R = 33K, and 20 pF, the time-constant will be
about 0.6 usec, which is pretty fast viz-a-viz the PIC's detecting
signals.
reposted - with [PIC]: thingie added
------------------------------------
Fernando wrote:
>Hi Bill,
>
>This is a general problem: the start-up of the power supplies with signals
>already applied to the chips. I have not yet a final solution, and would
>like to read other opinions.
Yes, this is a problem. The pullup clamping diodes on the PIC I/O pins
provide a sneak pathway for external signals to get onto the Vdd line,
and the PIC will be powered or partially powered. Then, when you turn
on the Vdd supply proper, the chip may not reset correctly. I try not
to do this, but others may have a hard solution. Adding a series R in
I/O will help, but may not solve this problem. A properly-designed
reset ckt may help here.
===============
>If you read the Ratings you will find (i have not here the data) about 5,5V
>and if Vin > Vcc, to protect the input clamping circuit, you must limit the
>current to < 20mA.
>If you use a resistor in series to limit the current to a few mA, in each
>input, I think ( not 100% sure ) you have protected the device. Of course R
>+ parasitic C is a filter and you are limiting the high frequency response.
I don't believe the RC due to parasitic C will matter very much, given
the frequency range of signals "normally" applied to a PIC. Assuming Cpara
of about 20 pF [high-estimate], and R = 3.3K, F3db = 1/(2*pi*R*C) = 2.4 Mhz.
Series R of 3.3K will protect the PIC to overvoltages in the range of
20 mA * 3.3K = 66V. However, it can also supply ~1.5 mA via the sneak
pathway described above.
Going with a much larger R = 33K, and 20 pF, the time-constant will be
about 0.6 usec, which is pretty fast viz-a-viz the PIC's detecting
signals.
> Yes, this is a problem. The pullup clamping diodes on the PIC I/O pins
> provide a sneak pathway for external signals to get onto the Vdd line,
> and the PIC will be powered or partially powered. Then, when you turn
> on the Vdd supply proper, the chip may not reset correctly. I try not
> to do this, but others may have a hard solution. Adding a series R in
> I/O will help, but may not solve this problem. A properly-designed
> reset ckt may help here.
I think some problems (latch-up?) are not cured by a reset. On my
breadboard circuits (powered by an 7805 or similar) I often just short the
power to achieve a guaranteed clean start....
Wouter
Wouter wrote:
>> Yes, this is a problem. The pullup clamping diodes on the PIC I/O pins
>> provide a sneak pathway for external signals to get onto the Vdd line,
>> and the PIC will be powered or partially powered. Then, when you turn
>> on the Vdd supply proper, the chip may not reset correctly. I try not
>> to do this, but others may have a hard solution. Adding a series R in
>> I/O will help, but may not solve this problem. A properly-designed
>> reset ckt may help here.
>
>I think some problems (latch-up?) are not cured by a reset. On my
>breadboard circuits (powered by an 7805 or similar) I often just short the
>power to achieve a guaranteed clean start....
Ah, the famous [and underutilized] crowbar - be it "manual" or
builtin cktry. Crowbar - the last resort of the thoroughly
thorough engineer.
In the case at hand, I am not sure the problem is "latchup", per
se, but rather the PIC is partially powered by the sneak pathway
and in some indeterminate state. So applying normal full power
doesn't reset it properly, but a reset ckt or PIC brownout feature
might work here <-- conjecture. Maybe someone else has actually
investigated this.
> In the case at hand, I am not sure the problem is "latchup", per
> se, but rather the PIC is partially powered by the sneak pathway
> and in some indeterminate state. So applying normal full power
> doesn't reset it properly, but a reset ckt or PIC brownout feature
> might work here <-- conjecture. Maybe someone else has actually
> investigated this.
But the crowbar (or removing the power and 'crowbarring' with 10 - 100 ohm)
will help against sneaky power too!
Wouter
Had the same problem once. I solved it using an external
TL7757C TI reset IC. Worked without any problems since then.
I haven't tried the brownout function of the PIC itself yet.
In those days, it wasn't implemented in the PICs I used.
