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'[PICLIST] 24Bit Up/Down Counter at 40 MHz'
2001\04\22@153928 by James Lee Williams

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Hello,

I am trying to implement a 512Kbyte external buffer using a 8bit
parrallel memory device.  However, I want to be able to control only the
following for addressing the bytes in the RAM.
1.  Clear Address Counter
2.  Increment Address Counter
3.  Decrement Address Counter

I want to use only these three signals coming from a pic to control the
addressing to the ram.  However, I can seem to find any counters with
this number of address lines.  Does anyone have any suggestions for
tackling this.  The reason for this, is that I want to be able to read
data from the ram in not more that 3 instruction cycles.

Also, maybe someone can also give me some suggestions on how to have
this ram accessable from two different pic devices.  One pic will only
write to the ram, while the other pic will only read from the ram.
However, I will in reality have to of these 512Kbyte chips, configured
in such a way that one pic can write to RAM of chip 1 while, at the same
time the other Pic will be able to read from chip 2.  The trick here is
that the the data buses much be able to be released from each Pic or
inserted.  But never both Pics at the same time.  I have been thinking
about using a dual bus transciever for each RAM chip.  Then use hardware
logic to prevent simaltaneous access to the same chip by both
controllers.  If anyone any clever ideas on this or comments, you input
would be greately appreciated.

Regards,

James

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2001\04\22@194348 by Dan Michaels

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At 09:29 PM 4/22/01 +0200, you wrote:
>Hello,
>
>I am trying to implement a 512Kbyte external buffer using a 8bit
>parrallel memory device.  However, I want to be able to control only the
>following for addressing the bytes in the RAM.
>1.  Clear Address Counter
>2.  Increment Address Counter
>3.  Decrement Address Counter
>

You might try searching the piclist archives - this sort of thing has
been discussed in the past. Tome Handley has done something like that.

For 40 mhz ops, you'll probably need to burn a gate array/etc if you
want to use only one chip, or use 4 or more 74AC16x series chips.

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2001\04\23@010852 by David W. Gulley

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James Lee Williams wrote:
> I want to use only these three signals coming from a pic to control the
> addressing to the ram.  However, I can seem to find any counters with
> this number of address lines.  Does anyone have any suggestions for
> tackling this.  The reason for this, is that I want to be able to read
> data from the ram in not more that 3 instruction cycles.

You can build up the counter with discrete logic, PALs or use a CPLD.

{Quote hidden}

You have not provided much information, regarding:
 will both PICs share the same address generator, (writes on PICa
   to be at same address as reads on PICb?)
 or will you have to control which PIC controls an address generator
   for each the two rams?
 could a single ram be "time sliced" such that during 1 phase PICa
   has access and during the next PICb?
 are there a cost/area/power limits on the design?
 what speed are the PICs running?
 what speed SRAM are you planning?



 A single SRAM and CPLD (or FPGA in the ~$10) range may be handle all
of the above (including data bus separation, dual counters PIC
arbitration, etc.).


David W. Gulley
Destiny Designs

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2001\04\23@091619 by James Lee Williams

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My PIC processors will be running at a full 20MHz.  Both SRAMS are to
have there own address generators, however I do not want the pics to
generate the actual address.  What I want the pics to do is just inform
the address generator logic to either increment the address point,
decrement it or reset it.  PICa will not be writing to the same bank as
PICb will be reading from, hence the reason for separate buses for the
RAM.  The reason for this, is that I must have as fast as possible
access to large amount of buffer ram.  This is for fast rastering motion
with a laser cutting system.  I'm talking in the order of 100 inch per
second * pixel resolution perfermance.

Regards,

James


{Original Message removed}

2001\04\23@102029 by Alan B. Pearce

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For the sort of speeds you are talking about I think you will need to find
some two port video ram, and have counters made from 74HC19x series devices.
I think the one you want is 74HC193 for the binary counter. There are four
devices which cover BCD/binary and Countup-Countdown/Count-direction in the
four possible combinations of these.

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2001\04\23@104907 by Andy Jancura

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Hello James,

look at Xilinx app. I think I saw there some implementation of dual acces
Ram on their chips.

Regards,

Andrej

p.s.: Excuse me please, I forgot the subject


------

My PIC processors will be running at a full 20MHz.  Both SRAMS are to
have there own address generators, however I do not want the pics to
generate the actual address.  What I want the pics to do is just inform
the address generator logic to either increment the address point,
decrement it or reset it.  PICa will not be writing to the same bank as
PICb will be reading from, hence the reason for separate buses for the
RAM.  The reason for this, is that I must have as fast as possible
access to large amount of buffer ram.  This is for fast rastering motion
with a laser cutting system.  I'm talking in the order of 100 inch per
second * pixel resolution perfermance.

Regards,

James

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2001\04\23@230805 by Tom Handley

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  James, I've done a couple of SRAM address generators for devices up to
512K using Lattice Semi's ispLSI1016x CPLDs. One is a parallel version for
use with 40-pin PICs where Port D is the data bus and Port E provides CS,
RD, and WD. The other uses an SPI-style serial bus. Both versions provide
external chip selects for other devices. In your case, it should be easy to
do using the same device. The 1016x family comes a 44-pin PLCC package (nice
for breadboarding) and a TSSOP package (about 1/4 the size).

  If you want to design your own CPLD, Lattice provides the ispDesignExpert
software with a free 6 month license which is easy to renew. This is an
incredibly powerful free software suite. It provides schematic, ABEL-HDL,
VHDL, and Verilog entry. Also included is a gate-level functional and timing
simulator with detailed timing analysis and a waveform viewer. There are too
many features to list here. The starter software supports their ispLSI (up
to 600 Macrocells), ispGAL, MACH (formerly Vantis), GAL, and PAL devices.
There is a large library of device models (gates, counters, etc). Using
schematic entry, you can add pre-defined modules or make your own from
another schematic or using one of the above HDL languages. Or, you can do
the whole thing in HDL.

  Programming the ISP (In-System-Programming) devices is trivial with just
a 5V supply. The Lattice software to do this is free and is included in the
ispDesignExpert package or as a separate ispDownload program. The buffered
ISP download cable uses a 74HC/LS367 and a few passives and connects to a PC
parallel port. Most folks already have the parts in their `stash'. To build
the Lattice ispDownload cable, and see some simple designs that have been
tested with a PIC, see my web page at:

     http://www.teleport.com/~thandley/Wilbure.htm

  For more information about Lattice Semiconductor's products and to
download the ispDesignExpert or ispDownload software, see:

     http://www.latticesemi.com

  - Tom

PSBS: I have a second factory-built buffered ISP Download cable that I'll
sell for $25 which includes shipping. Again, building one is trivial.

At 09:29 PM 4/22/01 +0200, James Lee Williams wrote:
{Quote hidden}

------------------------------------------------------------------------
Tom Handley
New Age Communications
Since '75 before "New Age" and no one around here is waiting for UFOs ;-)

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2001\04\24@051239 by Clive Frederickson

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Hi

If all you are doing is starting at the beginning of RAM then incrementing
through fill with data, How about FIFO's. They usually only need a couple of
control wires, Clock, Read, Write. They are dual ported and allow
simulations reading and writing. There is a little bit more to it than that,
But they are not difficult to drive.

Regards

Clive Frederickson
R&D Technician (CECF Group)

       ----------
       From:  James Lee Williams [SMTP:spam_OUTjawilliaTakeThisOuTspamCREDITVIEW.NO]
       Sent:  23 April 2001 14:16
       Subject:  Re: 24Bit Up/Down Counter at 40 MHz

       My PIC processors will be running at a full 20MHz.  Both SRAMS are
to
       have there own address generators, however I do not want the pics to
       generate the actual address.  What I want the pics to do is just
inform
       the address generator logic to either increment the address point,
       decrement it or reset it.  PICa will not be writing to the same bank
as
       PICb will be reading from, hence the reason for separate buses for
the
       RAM.  The reason for this, is that I must have as fast as possible
       access to large amount of buffer ram.  This is for fast rastering
motion
       with a laser cutting system.  I'm talking in the order of 100 inch
per
       second * pixel resolution perfermance.

       Regards,

       James


       {Original Message removed}

2001\04\24@053351 by Vasile Surducan

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Does any one know where to buy large FIFO's ( up to 2..3 Mb) in the East
of Europe?
Vasile

On Tue, 24 Apr 2001, Clive Frederickson wrote:

{Quote hidden}

>         {Original Message removed}

2001\04\24@063508 by Alan B. Pearce

face picon face
>Does any one know where to buy large FIFO's
>( up to 2..3 Mb) in the East of Europe?


Check out IDT. http://www.idt.com/products/fifo/Welcome.html I have used
some of their 1k Fifos, but have not checked their site for larger ones. I
see a selection guide as a PDF.

It is worth checking RS Components rshttp://www.com for these, that is where
I got the ones I used. I do not know how you get on for obtaining stuff from
them in Eastern Europe, but they may be worth a try.

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