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'[PICLIST] [sxtech] [SX]: "Real" IRQ driven I2C rou'
2002\01\17@054108 by Russell McMahon

picon face
> The last part of your description tells me that this 256kbit eeprom also
> uses 7-bit addressing.
> (7-bit meaning the id, 10-bit addressing is an extended i2c addressing
> mode).
> In my routines I have defined macros that access i2c devices like a stamp:
> I2cout id,address{\lowaddress},[dataout]
> I2cin id,address{\lowaddress},[datain]
> So I am pretty sure these routines can handle such an eeprom.

I'm confused :-).
I can't see how this could be "7 bit" addressing but if that's how someone
has defined it I am happy.

Please excuse the following "painful" description - you are clearly well
aware of IIC addressing etc but this may help others here wanting to use
this code.

I2C as provided in the original code sends a single byte write in 3 IIC bus
bytes as

   1010xyzW AAAAAAAA DDDDDDDD stop

1010 is device specific code
xyz USUALLY match the hardware strapping of 3 external address pins.
W is the read/write bit.
AAAAAAAA are the 8 address bits.
DDDDDDDD are the 8 data bits.
stop is STOP condition provided by cpu to indicate end of write sequence.

In the case of the 24C16 they cheat - the xyz bits are not compared to
hardware pins and are instead used as 3 extra TRUE address pins (even though
they may refer to them as bank bits). This means you can only have one such
IC in a given circuit. The hardware address pins are N/C.
The 11 bit address so formed may be addressed randomly between successive
writes. There is also a page mode allowing ??? bytes to be written
successively to a buffer.

The 24C256 addressing is

1010xyzW 0HHHHHHH LLLLLLLL DDDDDDDD stop

W as before
H is High address (7 bits)
L is low address (8 bits)

Any one of the 32k bytes may be addressed "randomly" on a given read or
write - to do this 15 address bits must be provided (7 + 8)
xyz are NOTIONALLY the same as before but NOW the 3 external device select
pins work and must match xyz for the EEROM to be addressed. xyz are now NOT
true address bits This allows up to 8 of them to be used in the same
circuit. Now xyz are NOT true address bits but are device select bits. This
device has a 64 byte page mode allowing up to 64 bytes to be written
successively for a single address write.
ie

           1010xyzW 0HHHHHHH LLLLLLLL DDDDDDDD DDDDDDDD
......................... DDDDDDDD stop

Note the 0 at the start of 0HHHHHHH - top bit is always zero.
This writes to an internal buffer and when the write is terminated the
buffer is written to the eerom proper. The EEROM will return a nack while
writing and performing reads is the formal way of establishing when the
write is completed - nacks will be returned to a read until writing is
complete.

The key thing here is, to change from small address devices to large address
devices you -

- Stop using xyz as true address bits
- Start using xyz as device select bits matching external chip-select pins
- Use two address bytes 0HHHHHHH LLLLLLLL in place of the single byte
AAAAAAAA
- QED




regards

               Russell McMahon

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2002\01\17@055844 by Alan B. Pearce

face picon face
>I'm confused :-).
>I can't see how this could be "7 bit" addressing but if that's how someone
>has defined it I am happy.

Check the Philips I2C spec document. The 7 bit addressing refers to the
first byte sent after the start condition. On a specific address in this
field a second address byte is sent which is also related to hardware
addressing, and between the two bytes can have a maximum 10 bit address.

Most EPROM's I have seen use the 7 bit address scheme with 4 bits fixed, and
3 bits strapped by external pins to allow a maximum of 8 EPROM's as you
describe. The 0HHHHHHH LLLLLLLL bytes you describe are data bytes, not
address bytes as far as the I2C spec goes, but are used within the EPROM as
an internal address, and have nothing to do with 7/10 bit addressing modes.

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