Post by thread:[PIC] using a counter in R-2R D to A converter

part 1 687 bytes content-type:text/plain; charset="iso-8859-1" (decoded quoted-printable) Tag added, PIC, in case it veers that way Off the top of my head, once the output of the counter passes 111 or 1111, the next o/p bit should toggle inverting logic I think 4 x XOR gates should do it. Each bit of low-order data from the counter goes to an A input, the logic control bit is commoned to the B inputs FYI - Attached is a circuit I use to make a variable AC voltage. The ADC pot changes the period of a timer. Output is a fairly good sine wave. Filter components depend on the frequency range for best output, although a constant-amplification amplifier could be added. My range for this circuit is quite low, 5 - 50Hz Joe part 2 7000 bytes content-type:image/gif; name="swell.gif" (decode) part 3 181 bytes content-type:text/plain; name="ATT00001.txt" (decoded base64) -- http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at mailman.mit.edu/mailman/listinfo/piclist

Just to point out that your circuit is not R-2R. In a true R-2R circuit, as the name implies, half of the resistors have values of 1 x some resistance and the other half have 2 x that resistance, in a "ladder like" arrangement. Isaac Em 17/5/2012 06:44, IVP escreveu: {Quote hidden}> Tag added, PIC, in case it veers that way > > Off the top of my head, once the output of the counter passes 111 > or 1111, the next o/p bit should toggle inverting logic > > I think 4 x XOR gates should do it. Each bit of low-order data from > the counter goes to an A input, the logic control bit is commoned to > the B inputs > > FYI - > > Attached is a circuit I use to make a variable AC voltage. The ADC > pot changes the period of a timer. Output is a fairly good sine wave. > Filter components depend on the frequency range for best output, > although a constant-amplification amplifier could be added. My range > for this circuit is quite low, 5 - 50Hz > > Joe > > > > > ----- > Nenhum vírus encontrado nessa mensagem. > Verificado por AVG - http://www.avgbrasil.com.br > Versão: 10.0.1424 / Banco de dados de vírus: 2425/5005 - Data de Lançamento: 05/17/12

I'd be curious as to how you will generate the rising form, but... Let's say you use a 74HC238 to decode the counter. A resistor connected to each output that represents the sin of the angle. All resistors tied together and going to the - input of an op-amp. A feedback resistor around the op-amp (output to - input). The + input could be switched by bit 4 to go from ground to Vmax. When the count is 7, the op-amp would put out, say -3V. On the next count, the 238 would put out 0, the + input of the op-amp would be +3V and the output would be -3V, and start going down as the count goes up. When the count reaches 7 again, the op-amp would put out 0V. When it rolls over again, the + input returns to 0V, and the op-amp will still output 0V. Does that make sense? Kerry Lachlan Mac Donald wrote: > Hi! Does anyone know of a simple way to use an upcounter (not up/down ) > counter to generate a sine wave . No problem generating the rising > section,but can't think of a simple way to generate the falling > section.Only needs to be 3 or 4 bit,happy to use diode logic, or switch a > transistor.I do have the next counter stage output, so can use this to > toggle etc if required.Any thoughts appreciated,thank you. Lach >

At 05:44 AM 17/05/2012, you wrote: >Tag added, PIC, in case it veers that way The classic way to do this is with a Johnson counter. See AoE figure 9.93 for an implementation using a 4015 and an inverter that yields a 16-level approximation to a sine wave. {Quote hidden}>Off the top of my head, once the output of the counter passes 111 >or 1111, the next o/p bit should toggle inverting logic > >I think 4 x XOR gates should do it. Each bit of low-order data from >the counter goes to an A input, the logic control bit is commoned to >the B inputs > >FYI - > >Attached is a circuit I use to make a variable AC voltage. The ADC >pot changes the period of a timer. Output is a fairly good sine wave. >Filter components depend on the frequency range for best output, >although a constant-amplification amplifier could be added. My range >for this circuit is quite low, 5 - 50Hz > >Joe Trivial to do with a PIC. Just generate an interrupt, spit out the new number, increment the pointer to your table modulo 256 (say), look up the next number, and set your comparator for the next interrupt. Your interrupts will be at your sine wave frequency * 256, so with a 200ns timer resolution you'll get a resolution of about 0.25Hz at 50Hz. PICs (at least the smaller ones) have constant interrupt latency so this is feasible without extra parts or jitter. If there was variable latency and the jitter was excessive, you could make a pin toggle right at the comparator hit and clock an external buffer (pipelined, obviously). Another part. If I had to that, I'd probably use an HC595 and use a serial output from the PIC (the 595 is a serial-to- parallel SR with an edge-triggered output buffer). There are other techniques (phase accumulator) that can be used to improve resolution with a relatively modest clock rate (at the expense of more complexity and some jitter), but maybe you don't need to do that. Best regards,

Hi!Thank you everybody for your replies.The circuit has to be simple,and easily adjusted in the field.The output is a tone in the audio speech range,suitable for radio or landline transmission.The freq is critical,and the pic reads this at the base.To generate the tone,a 4060 is to be used, and the oscillator will be able to use small value,stable cap and a resistor (multiturn trimpot).Original plan was to generate a square wave at the desired freq. at the end of the counter chain .I had hoped to use a higher starting oscillator freq and R-2R network to generate a sine wave.Thoughts are now to do this for the rising half wave,use the output of the next stage of the counter to isolate the counter output for the falling half, and have a capacitor (that charged up during the rising half) discharge to give a rough output for the falling half. Very rough,but still better than just the square wave.It is important a tech with a multimeter can check and adjust the freq in the field,and a lot of multimeters have built in freq reading ability.The problem is I am trying to kludge a down counter for the falling half of the sinewave! On Fri, May 18, 2012 at 2:23 AM, Spehro Pefhany <spam_OUTspeffTakeThisOuTinterlog.com> wrote: {Quote hidden}> At 05:44 AM 17/05/2012, you wrote: > >Tag added, PIC, in case it veers that way > > The classic way to do this is with a Johnson counter. See > AoE figure 9.93 for an implementation using a 4015 > and an inverter that yields a 16-level approximation to a > sine wave. > > >Off the top of my head, once the output of the counter passes 111 > >or 1111, the next o/p bit should toggle inverting logic > > > >I think 4 x XOR gates should do it. Each bit of low-order data from > >the counter goes to an A input, the logic control bit is commoned to > >the B inputs > > > >FYI - > > > >Attached is a circuit I use to make a variable AC voltage. The ADC > >pot changes the period of a timer. Output is a fairly good sine wave. > >Filter components depend on the frequency range for best output, > >although a constant-amplification amplifier could be added. My range > >for this circuit is quite low, 5 - 50Hz > > > >Joe > > Trivial to do with a PIC. Just generate an interrupt, spit > out the new number, increment the pointer to your table > modulo 256 (say), look up the next number, and set your > comparator for the next interrupt. Your interrupts will be > at your sine wave frequency * 256, so with a 200ns timer > resolution you'll get a resolution of about 0.25Hz at 50Hz. > PICs (at least the smaller ones) have constant interrupt > latency so this is feasible without extra parts or jitter. > If there was variable latency and the jitter was excessive, > you could make a pin toggle right at the comparator hit > and clock an external buffer (pipelined, obviously). Another > part. If I had to that, I'd probably use an HC595 and > use a serial output from the PIC (the 595 is a serial-to- > parallel SR with an edge-triggered output buffer). > > There are other techniques (phase accumulator) that can be > used to improve resolution with a relatively modest clock > rate (at the expense of more complexity and some jitter), > but maybe you don't need to do that. > > Best regards, > >

Hi!Thank you,and all the best with the 4600.I remember the excitement when it came out!Using 4060 so I can use small,stable capacitor and could have final output freq down to 50Hz.Also easier and quicker to set a freq in kHz range accurately and have better precision at output freq..Plus one chip only rqd.Also considered a 567.Thank you On Fri, May 18, 2012 at 9:58 AM, IVP <.....joecolquittKILLspam@spam@clear.net.nz> wrote: {Quote hidden}> To generate the tone, a 4060 is to be used >> > > Why not an opamp or 4046 ? > > You mentioned diode shaping. I'm currently overhauling my > ETI 4600 synthesiser. Its primary oscillator outputs are opamp > derived triangle waves. These are clipped => square waves and > passed through the attached => sine > > Joe >

Why don't you generate the sine wave directly with a PIC??? -- Bob Ammerman RAm Systems ----- Original Message ----- From: "Lachlan Mac Donald" <lachmacKILLspamgmail.com> To: "Microcontroller discussion list - Public." <.....piclistKILLspam.....mit.edu> Sent: Thursday, May 17, 2012 7:24 PM Subject: Re: [PIC] using a counter in R-2R D to A converter {Quote hidden}> Hi!Thank you everybody for your replies.The circuit has to be simple,and > easily adjusted in the field.The output is a tone in the audio speech > range,suitable for radio or landline transmission.The freq is critical,and > the pic reads this at the base.To generate the tone,a 4060 is to be used, > and the oscillator will be able to use small value,stable cap and a > resistor (multiturn trimpot).Original plan was to generate a square wave > at > the desired freq. at the end of the counter chain .I had hoped to use a > higher starting oscillator freq and R-2R network to generate a sine > wave.Thoughts are now to do this for the rising half wave,use the output > of > the next stage of the counter to isolate the counter output for the > falling half, and have a capacitor (that charged up during the rising > half) > discharge to give a rough output for the falling half. Very rough,but > still > better than just the square wave.It is important a tech with a multimeter > can check and adjust the freq in the field,and a lot of multimeters have > built in freq reading ability.The problem is I am trying to kludge a down > counter for the falling half of the sinewave! > > On Fri, May 18, 2012 at 2:23 AM, Spehro Pefhany <EraseMEspeffspam_OUTTakeThisOuTinterlog.com> > wrote: > >> At 05:44 AM 17/05/2012, you wrote: >> >Tag added, PIC, in case it veers that way >> >> The classic way to do this is with a Johnson counter. See >> AoE figure 9.93 for an implementation using a 4015 >> and an inverter that yields a 16-level approximation to a >> sine wave. >> >> >Off the top of my head, once the output of the counter passes 111 >> >or 1111, the next o/p bit should toggle inverting logic >> > >> >I think 4 x XOR gates should do it. Each bit of low-order data from >> >the counter goes to an A input, the logic control bit is commoned to >> >the B inputs >> > >> >FYI - >> > >> >Attached is a circuit I use to make a variable AC voltage. The ADC >> >pot changes the period of a timer. Output is a fairly good sine wave. >> >Filter components depend on the frequency range for best output, >> >although a constant-amplification amplifier could be added. My range >> >for this circuit is quite low, 5 - 50Hz >> > >> >Joe >> >> Trivial to do with a PIC. Just generate an interrupt, spit >> out the new number, increment the pointer to your table >> modulo 256 (say), look up the next number, and set your >> comparator for the next interrupt. Your interrupts will be >> at your sine wave frequency * 256, so with a 200ns timer >> resolution you'll get a resolution of about 0.25Hz at 50Hz. >> PICs (at least the smaller ones) have constant interrupt >> latency so this is feasible without extra parts or jitter. >> If there was variable latency and the jitter was excessive, >> you could make a pin toggle right at the comparator hit >> and clock an external buffer (pipelined, obviously). Another >> part. If I had to that, I'd probably use an HC595 and >> use a serial output from the PIC (the 595 is a serial-to- >> parallel SR with an edge-triggered output buffer). >> >> There are other techniques (phase accumulator) that can be >> used to improve resolution with a relatively modest clock >> rate (at the expense of more complexity and some jitter), >> but maybe you don't need to do that. >> >> Best regards, >> >> -