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'[PIC] strange bugs and debugging using ICD2 for 12'
2005\09\14@052844 by Chen Xiao Fan

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Now I am working on a PIC firmware using 12F629. I am using
the internal comparators and the internal comparator
reference. There are a bug that under certain conditions,
the CMIF flag will stay at 1 even though it should be 0.

After some time of manual debugging using a debugging pin,
I decide to use ICD2 with the debug header.

When running continuously using ICD2, I can repeat the bug.
Once I halt the processor, I know that CMIF flag is still 1.
Then I let the processor run again, the CMIF flag is correctly
changed to 0 and stay at 0 and I can not repeat the bug any
more. That is very strange.

The same thing happen when I set a break point, once the
program halt, the bug is gone. Very very strange.

What could cause the problem? Thanks in advance.

Regards,
Xiaofan

2005\09\15@070638 by Xiaofan Chen

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Seems that I need to clear CMIF flag and read the CMCON register
(to clear the mismatch conditon in the datasheet) to really clear the
CMIF flag. Still I am not so sure about the ICD2 behavious. Anyway
the behaviour of the comparator is quite strange for this 12F629.
I've sent an email to Dan Butler of Microchip SMTD division to ask
for more information. The description of the datasheet is not
really very clear.

Regards,
Xiaofan

2005\09\15@071925 by Michael Rigby-Jones

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>-----Original Message-----
>From: spam_OUTpiclist-bouncesTakeThisOuTspammit.edu [.....piclist-bouncesKILLspamspam@spam@mit.edu]
>Sent: 15 September 2005 12:07
>To: Microcontroller discussion list - Public.
>Subject: Re: [PIC] strange bugs and debugging using ICD2 for 12F629
>
>
>Seems that I need to clear CMIF flag and read the CMCON
>register (to clear the mismatch conditon in the datasheet) to
>really clear the CMIF flag. Still I am not so sure about the
>ICD2 behavious. Anyway the behaviour of the comparator is
>quite strange for this 12F629. I've sent an email to Dan
>Butler of Microchip SMTD division to ask for more information.
>The description of the datasheet is not really very clear.

You need to do it in the opposite order, i.e. read (or write) the CMCON register to clear the mismatch, and then clear the CMIF interrupt flag.  If you clear the CMIF bit first, it will immediately get set again by the mismatch condition.  This is very simmilar to the PORTB interrupt on change peripheral in other PIC's.

Regards

Mike

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2005\09\15@074038 by Xiaofan Chen

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Hi Mike,

Yes that is exactly the correct sequence.

Still why the bug is gone after ICD2 halt is very strange! Maybe when ICD2
got halt, the CMCON got read out.

Another thing is that once the signal is removed, COUT should stay at 0
and why the CMIF flag stays 1?

What does really a "mismatch condition" really mean?
How long will CMIF flag be set after signal changes? It seems to me
COUT flag is asynchronous to the system clock. How about CMIF?
What I do here is really timing critical and every microsecond counts.
I am using the 4Mhz internal oscillator and each instruction is 1us. My
signal is less than 4us and the period is about 100us.

Regards,
Xiaofan

2005\09\15@074631 by olin piclist

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Xiaofan Chen wrote:
> Seems that I need to clear CMIF flag and read the CMCON register
> (to clear the mismatch conditon in the datasheet) to really clear the
> CMIF flag. Still I am not so sure about the ICD2 behavious. Anyway
> the behaviour of the comparator is quite strange for this 12F629.
> I've sent an email to Dan Butler of Microchip SMTD division to ask
> for more information. The description of the datasheet is not
> really very clear.

Keep in mind that the ICD2 does a read of the register if it is displaying
it in MPLAB.  This can make things seem strange for registers where reading
has a side effect.  Some examples are reading RCREG clears the RCIF flag,
reading port B clears the changed condition, and there are others.


*****************************************************************
Embed Inc, embedded system specialists in Littleton Massachusetts
(978) 742-9014, http://www.embedinc.com

2005\09\15@080540 by Xiaofan Chen

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Thanks for the explanations Olin. It is a pain to use ICD2 debugging though.
I really missed the days of ICE2000. Hopefully next time when we use PIC
again I can buy the emulator processor module.

Does ICE2000 need to read internal registers in order to display them
in MPLAB?

Anyway it seems that the nexrt project in PIC will be next year since
other current projects are now using Silicon Labs C8051F due to the fact
that Microchip comes out the 4mmx4mm QFN packages only this year and we
will not consider anything bigger than 5mmx5mm.

Regards,
Xiaofan

2005\09\15@081000 by Andrew

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On Thu, 15 Sep 2005, Xiaofan Chen wrote:

> What does really a "mismatch condition" really mean?

The way I've always imagined it working is that each register that
supports IOC has a cache. Whenever you read or write the register the
processor also populates this cache. Every cycle the cache and the
register are compared and if they are different (aka a mismatch condition)
then an interupt is raised.

Thats why, to stop an interupt imeadiatley reoccuring you need to read or
write the register, and so repopulate the cache, before reseting its
interrupt flag.

I don't know if that is _really_ how it is implemented but thats how I
thought about it when I first came across it.

HTH,

Andrew

2005\09\15@081616 by Michael Rigby-Jones

picon face


{Quote hidden}

That's pretty much how it works.  The "cache" is simply a data latch that is clocked by a read or write.  The datasheet shows the actual block diagram of the peripheral.

Regards

Mike

=======================================================================
This e-mail is intended for the person it is addressed to only. The
information contained in it may be confidential and/or protected by
law. If you are not the intended recipient of this message, you must
not make any use of this information, or copy or show it to any
person. Please contact us immediately to tell us that you have
received this e-mail, and return the original to us. Any use,
forwarding, printing or copying of this message is strictly prohibited.
No part of this message can be considered a request for goods or
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2005\09\15@083909 by Xiaofan Chen

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Thanks Andrew and Mike.

We also read the datasheet very carefully this time and found the bug
by this way. Still there must be something missing in the the block diagram.
I actually got the local Microchip FAE to the office. We could not find where
is the system clock in the diagram. I guess the CMIF flag should be
synchronized somewhat to the system clock but COUT is not.
The exact time of the CMIF flag gets set will affect the performance of the
product I develop...

Regards,
Xiaofan

On 9/15/05, Michael Rigby-Jones <EraseMEMichael.Rigby-Jonesspam_OUTspamTakeThisOuTbookham.com> wrote:
>
That's pretty much how it works.  The "cache" is simply a data latch
that is clocked by a read or write.  The datasheet shows the actual
block diagram of the peripheral.
>
> Regards
>
> Mike

2005\09\15@102206 by olin piclist

face picon face
Xiaofan Chen wrote:
> Does ICE2000 need to read internal registers in order to display them
> in MPLAB?

Yes, it has the same issue.  Most of the time this is easy to get around by
not adding the particular SFR to the watch window.  It's pretty rare you
need to watch a SFR, especially one were reading has side effects.


*****************************************************************
Embed Inc, embedded system specialists in Littleton Massachusetts
(978) 742-9014, http://www.embedinc.com

2005\09\15@220549 by Chen Xiao Fan

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Hi all,

The following is the reply from Microchip USA. This is one
of the reason I like Microchip. The support is excellent!
I still need to read more into the reply though. Anyway I
think it is good to share this info to the list so people
will not make similar mistakes as I. The datasheet is
DS41190C and Figure 6-4 is on page 38.

Regards,
Xiaofan

----------------------------------------------
Xiaofan Chen
R&D Engineer, Photoelectric Sensor Development
Pepperl+Fuchs Singapore
http://www.pepperl-fuchs.com
Signals for the world of automation
--------------------------------------------


---- How Comparator in 12F629 works and CMIF and COUT flag-------

The comparator mismatch circuit consists of two latches. A "mismatch
condition" is defined as the condition when the output of one latch
is different than the output of the other latch.

Any write to a register is performed as a read-modify-write.  

For example: the operation (MOVWF   Register) first reads the Register,
does nothing with it, and then writes the contents of W to the Register.

A comparator mismatch condition is cleared by the action of reading the
CMCON register. Since a write operation also performs a read
(read-modify-write) either a read or write operation will clear
the mismatch condition because both perform the required read.

Now consider the mismatch circuit. There are two latches that make
up the mismatch circuit (see data sheet figure 6-4). When the EN
input is high, the latch is transparent, and when the EN input is
low the Q output is held to the state the D input was in at the
moment the EN signal transitioned to the low state.

In Figure 6-4 the bottom latch EN input is controlled by RD CMCON
and the top latch EN input is controlled by (NOT)RD CMCON. Normally
RD CMCON is low (CMCON is not being read) so the top latch is
normally transparent and the bottom latch is normally held. When
CMCON is read, the top latch is held momentarily for the read and
the bottom latch is opened up to accept the present state of the
comparator output. Immediately after CMCON is read the RD CMCON
signal goes low and the bottom latch goes back to being held
while the top latch goes back to being transparent. At this
moment both latches have the same signal level at the Q output,
which is the state of the comparator at the moment the RD CMCON
signal terminated.

When the comparator inputs change such that the comparator output
changes, the top transparent latch lets that signal through to the
mismatch exclusive-or. The different levels at the bottom latch's
Q output and the top transparent latch's Q output will cause the
exclusive-or output to go high thereby setting the CMIF interrupt
bit. If the comparator output returns to the previous state, the
latch Q outputs (exclusive-or inputs) will return to the same logic
level thereby removing the "Set CMIF bit" signal but this will not
reset the CMIF interrupt bit because there is a third latch not shown
in the diagram which holds the CMIF interrupt until it is cleared by
software. For example BCF PIR1,CMIF.

Now, consider that there are two comparator changes that can be sensed:
One when the comparator goes from low to high, and the other when the
comparator goes from high to low. If the CMCON register is read when
the comparator is low, both mismatch latch Q outputs will be low
immediately after the read and the mismatch circuit will be armed for
sensing a low to high change. Suppose that the comparator goes from
low to high. The upper transparent latch Q output will immediately go
high and set the CMIF bit. Now consider that before the CMCON register
can be read the comparator goes low again. If this occurs, the upper
transparent latch Q output will immediately return to the low state
matching the bottom latch Q output. Both latch's Q outputs will be
low and armed to catch another low to high change. In this case the
mismatch condition cleared itself so there is no need to read CMCON.

What this means is that the proper method for clearing the CMIF interrupt
depends on what you are trying to do.

Method 1.
If you are trying to catch only low to high transitions then read the CMCON
register when the comparator output is low and do not read it again. The
CMIF
will go high when a low to high change occurs. If you try to clear the CMIF
bit while the comparator is still high it will not respond because the
mismatch
latch condition still exists. If you cannot clear the CMIF bit that means
the
comparator output is still high. You will know when the comparator output
goes
low because the CMIF bit will respond to a clear command.

In summary, to sense only low to high transitions (or high to low) you need
to:

1. Read the CMIF bit and sense that it is high
2. Try to clear the CMIF bit (bcf PIR1,CMIF)
3. Read the CMIF bit: if it is 1 then repeat step 2

Method 2.
If you are trying to catch both the low to high transition and the high to
low
transition then you need to read the CMCON register to re-arm the mismatch
latches for both conditions. This means that the comparator output must be
stable at the high state for at least as long as it takes to recognize the
low to high change and read the CMCON register which will set the bottom
latch. After the CMCON register is read you will be able to reset the CMIF
interrupt bit, but only if the comparator output is still high.

In summary, to sense both transitions you need to:

1. Read the CMIF bit and sense that it is high
2. Read the CMCON register to clear the mismatch condition
3. Clear the CMIF bit to clear the interrupt

The comparator output must remain stable for the entire sequence.

Finally, why does using the ICD seem to clear the bug? If you have a watch
window
open or are monitoring register values with the ICD, when the ICD breaks or
pauses,
all the registers in the watch window or register display are updated with
information from the device. Upon break or pause the MPLAB software performs

reads in the background and updates the display with the new values. This
reading
action will affect the state of the mismatch latch hardware in the same
manner
as performing reads during program execution.

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