Post by thread:[PIC] instrction cycle

I have a small delay subroutine in my code: ..... call delay .... delay nop nop nop return Now I want to replace the 'call delay' with some 'nop's. How many 'nop' should I use so the program will run same time as the 'call delay'? I know a 'call' equals 2 'nop's. what about the 'return'? ____________________________________________

> I have a small delay subroutine in my code: > > ..... > call delay > .... > > delay > nop > nop > nop > return > > Now I want to replace the 'call delay' with some 'nop's. > How many 'nop' should I use so the program will run same time > as the 'call > delay'? I know a 'call' equals 2 'nop's. what about the 'return'? Two NOP's for the "CALL" and 2 for the "RETURN" (plus the three already there). I just looked in a number of data sheets, and everyone said "2 cycles" for RETURN. What did *your* data sheet say ?? Best Regards, Jan-Erik. ____________________________________________

On Thu, 2004-12-09 at 11:09 -0500, Jianhua Zhang wrote: > I have a small delay subroutine in my code: > > ..... > call delay > .... > > delay > nop > nop > nop > return > > Now I want to replace the 'call delay' with some 'nop's. > How many 'nop' should I use so the program will run same time as the 'call > delay'? I know a 'call' equals 2 'nop's. what about the 'return'? Anything that writes to the PC will result in a pipeline flush, which means 2 cycles. Since the return also modifies the PC it will result in two cycles as well. TTYL ----------------------------- Herbert's PIC Stuff: http://repatch.dyndns.org:8383/pic_stuff/ ____________________________________________

return takes 2 also. Jianhua Zhang wrote: > I have a small delay subroutine in my code: > > ..... > call delay > .... > > delay > nop > nop > nop > return > > Now I want to replace the 'call delay' with some 'nop's. > How many 'nop' should I use so the program will run same time as the 'call > delay'? I know a 'call' equals 2 'nop's. what about the 'return'? > > > ______________________________________________

----- Original Message ----- From: "Jianhua Zhang" <.....jzhangKILLspam@spam@icmcontrols.com> Subject: [PIC] instrction cycle > Now I want to replace the 'call delay' with some 'nop's. > How many 'nop' should I use so the program will run same time as the 'call > delay'? I know a 'call' equals 2 'nop's. what about the 'return'? ANYTHING that changes the program counter takes 2 cycles. --McD ____________________________________________

On Thu, 2004-12-09 at 11:48 -0500, John J. McDonough wrote: > ----- Original Message ----- > From: "Jianhua Zhang" <jzhangKILLspamicmcontrols.com> > Subject: [PIC] instrction cycle > > > > Now I want to replace the 'call delay' with some 'nop's. > > How many 'nop' should I use so the program will run same time as the 'call > > delay'? I know a 'call' equals 2 'nop's. what about the 'return'? > > ANYTHING that changes the program counter takes 2 cycles. Note it doesn't need the CHANGE the program counter, all it takes is a WRITE to the program counter. TTYL ----------------------------- Herbert's PIC Stuff: http://repatch.dyndns.org:8383/pic_stuff/ ____________________________________________

At 09:09 AM 12/9/2004, Jianhua Zhang wrote: >I have a small delay subroutine in my code: > >..... >call delay >.... > >delay > nop > nop > nop > return > >Now I want to replace the 'call delay' with some 'nop's. >How many 'nop' should I use so the program will run same time as the 'call >delay'? I know a 'call' equals 2 'nop's. what about the 'return'? Others have already mentioned that call and return both require 2 cycles each. But I'm curious: why do you want to eliminate the subroutine call. Are you running out of stack space? If you wanted to achieve the same delay as multiple nop commands but use less code space (and not need any stack space), you could also replace pairs of NOP commands with "goto $+1" so long as you don't cross any 2k page boundaries. In other words, nop nop nop nop nop nop nop is the same as: goto $+1 goto $+1 goto $+1 nop This is an old trick first mentioned by Andy Warren and is one of those brilliant tricks that seem obvious once you've seen it. The problem is seeing that first time! dwayne -- Dwayne Reid <.....dwaynerKILLspam.....planet.eon.net> Trinity Electronics Systems Ltd Edmonton, AB, CANADA (780) 489-3199 voice (780) 487-6397 fax Celebrating 20 years of Engineering Innovation (1984 - 2004) .-. .-. .-. .-. .-. .-. .-. .-. .-. .- `-' `-' `-' `-' `-' `-' `-' `-' `-' Do NOT send unsolicited commercial email to this email address. This message neither grants consent to receive unsolicited commercial email nor is intended to solicit commercial email. ____________________________________________

Dwayne Reid wrote: > If you wanted to achieve the same delay as multiple nop commands but use > less code space (and not need any stack space), you could also replace > pairs of NOP commands with "goto $+1" so long as you don't cross any 2k > page boundaries. In other words, > > nop > nop > nop > nop > nop > nop > nop > > is the same as: > > goto $+1 > goto $+1 > goto $+1 > nop And to make this even easier, you can use my WAITNOP macro in STD.INS.ASPIC at http://www.embedinc.com/pic. It automatically writes GOTO $+1 when it can, and takes care of the odd cycle case. You only specify how many instruction cycles you want it to waste. ***************************************************************** Embed Inc, embedded system specialists in Littleton Massachusetts (978) 742-9014, http://www.embedinc.com ____________________________________________

part 1 597 bytes content-type:text/plain (decoded 7bit) On Thu, 2004-12-09 at 15:53 -0300, Mauricio Jancic wrote: > What about ADDWF PCL, F ?? > It takes only 1 cicle, the datasheet says... But it doesn't, I just sim'd it and it clearly uses two cycles. Very interesting, MChip has "note 3" on the instruction set summary, but doesn't apply it to that instruction. On the page before it only mentions if PC is MODIFIED by an instruction does it take two cycles. I've attached the results of sim. TTYL ----------------------------- Herbert's PIC Stuff: http://repatch.dyndns.org:8383/pic_stuff/ part 2 25072 bytes content-type:image/gif; name=addwf_0.gif (decode) part 3 25028 bytes content-type:image/gif; name=addwf_1.gif (decode) part 4 79 bytes content-type:text/plain; charset="us-ascii" (decoded 7bit) ____________________________________________

----- Original Message ----- From: "Mauricio Jancic" <infospam_OUTjanso.com.ar> Subject: RE: [PIC] instrction cycle > What about ADDWF PCL, F ?? > It takes only 1 cicle, the datasheet says... I seem to remember seeing that and I don't believe it. Here's the deal ... while the processor is executing an instruction, it is also reading the next instruction so that it doesn't have to wait for it when it's day comes. If an instruction writes the the PC, the instruction just read is no longer valid, so another cycle is wasted getting the next instruction. An ADD instruction only takes one cycle, but if you have modified the PCL you need to burn another cycle to fetch the next instruction since the pipeline is now invalid. So it's really not totally correct to say that call, goto, and return (as well as all those instructions that might skip, but only when they do!) take 2 cycles. They only take one cycle, but they force the processor to burn another cycle waiting for the pipeline. So really, it's not the goto that takes 2 cycles, it's the instruction that gets executed after the goto. Herbert made the point that it is the writing to the PC, not necessarily changing it, that causes the pipeline to be invalidated. I could imagine an optimization where the chip would recognize when the write changed the PC and not invalidate the pipeline for an instruction like goto $+1, but think of how much harder that would make it to figure out how long a routine would take ... and it would only rarely be an improvement. --McD ____________________________________________

Mauricio Jancic wrote: > What about ADDWF PCL, F ?? > It takes only 1 cicle, the datasheet says... The data sheet probably says that ADDWF only takes one cycle, usually. I'm sure it also mentions that modifications of PC causes an extra cycle due to the instruction pipeline being flushed. ***************************************************************** Embed Inc, embedded system specialists in Littleton Massachusetts (978) 742-9014, http://www.embedinc.com ____________________________________________

At 11:53 AM 12/9/2004, Mauricio Jancic wrote: >What about ADDWF PCL, F ?? >It takes only 1 cicle, the datasheet says... Can you let us (or better yet, Microchip) know the exact filename of that manual. The above is an error and should be corrected. dwayne -- Dwayne Reid <@spam@dwaynerKILLspamplanet.eon.net> Trinity Electronics Systems Ltd Edmonton, AB, CANADA (780) 489-3199 voice (780) 487-6397 fax Celebrating 20 years of Engineering Innovation (1984 - 2004) .-. .-. .-. .-. .-. .-. .-. .-. .-. .- `-' `-' `-' `-' `-' `-' `-' `-' `-' Do NOT send unsolicited commercial email to this email address. This message neither grants consent to receive unsolicited commercial email nor is intended to solicit commercial email. ____________________________________________

Dwayne Reid wrote : > nop > nop > nop > nop > nop > nop > nop > > is the same as: > > goto $+1 > goto $+1 > goto $+1 > nop Or : call wait4cycles ; 4 cycles goto $+1 ; 2 cycles nop ; 1 cycle Then put the "wait4cycles" label right before the return in an *existing* subroutine. No extra code for that. Both this one and the "goto $+1" one are described in the "Tips ?n Tricks" manual (DS40040B). Tip #15, b.t.w. Jan-Erik. ____________________________________________

>>So really, it's not >>the goto that >>takes 2 cycles, it's the instruction that gets executed after >>the goto. Yes, that's what I thought. I *knew* (always supposed) that the ADDWF PCL would take 2 cycles, but the datasheet doesn't says so explicitly. That second instruction that you mentioned is a NOP as mentioned in note 3 on the instruction table on any datasheet. Bye! Mauricio Jancic Janso Desarrollos Microchip Consultant Program Member (54) 11-4542-3519 KILLspaminfoKILLspamjanso.com.ar http://www.janso.com.ar >>{Original Message removed}

On Thu, 2004-12-09 at 15:13 -0500, Olin Lathrop wrote: > Mauricio Jancic wrote: > > What about ADDWF PCL, F ?? > > It takes only 1 cicle, the datasheet says... > > The data sheet probably says that ADDWF only takes one cycle, usually. I'm > sure it also mentions that modifications of PC causes an extra cycle due to > the instruction pipeline being flushed. It does, but adding "zero" to something isn't a modification, which is the point I'm trying to make. I personally believe the wording should be changed to any WRITE to the PC will cause two cycles, since you don't need to mod it to cause two cycles to be needed. If one remembers WHY two cycles are needed it makes perfect sense, but to someone relying only on exactly what the datasheet says (yes, I know, something very dangerous! :) ) then I'd say the datasheet is wrong. TTYL ----------------------------- Herbert's PIC Stuff: http://repatch.dyndns.org:8383/pic_stuff/ ____________________________________________

On Thu, 2004-12-09 at 13:19 -0700, Dwayne Reid wrote: > At 11:53 AM 12/9/2004, Mauricio Jancic wrote: > >What about ADDWF PCL, F ?? > >It takes only 1 cicle, the datasheet says... > > Can you let us (or better yet, Microchip) know the exact filename of that > manual. The above is an error and should be corrected. Both the latest 16F628 and 16F877 datasheets contain the same wording. Some might not consider it "wrong" outright, I would consider it "incomplete". TTYL ----------------------------- Herbert's PIC Stuff: http://repatch.dyndns.org:8383/pic_stuff/ ____________________________________________

It doesn't EXPLICITLY said that "ADDWF PCL, F Takes 1 cycle", but if you take a look at the instruction table (on the instruction set section or the reference manual for the midrange) you'll see that it says that ADDWF takes 1 cycle and there is no mention (there, like the one on the BTFSx) that that instruction will take 2 cycles when the PCL is modified... Mauricio Jancic Janso Desarrollos Microchip Consultant Program Member (54) 11-4542-3519 RemoveMEinfoTakeThisOuTjanso.com.ar http://www.janso.com.ar >>{Original Message removed}

> >What about ADDWF PCL, F ?? > >It takes only 1 cicle, the datasheet says... > > Can you let us (or better yet, Microchip) know the exact > filename of that manual. The above is an error and should > be corrected. And don't bother pointing us to the *generic* ADDWF command. That part says 1 cycle in all data sheets I know about. No, show as where it says that the command *exactly* as shown above ("ADDWF PCL, F") takes just 1 cycle... Regards, Jan-Erik. ____________________________________________

> Yes, that's what I thought. I *knew* (always supposed) that > the ADDWF PCL would take 2 cycles... Hm, well, yes and no... :-) Only "ADDWF PCL, F" takes two cycles, "ADDWF PCL, W" takes, AFAIK, 1 cycle. > but the datasheet doesn't says so explicitly. Well, in a way they do, but not in the description of the ADDWF instruction. :-) Jan-Erik. ____________________________________________

>>Well, in a way they do, but not in the description of the >>ADDWF instruction. :-) That's my point. When the mention the BTFSx the say that it will take 2 cycles under certain circumstances, but they not advice that on the other instructions that might modify the PCL register. Also, if you take a look at the beginning of the datasheet, under "loading of PC in different situations" (is on most datasheet, for example, page 28 od DS40044B PIC16f62xA/648A) there is no mention that a "computed goto" will take two cycles. Of course I'm not saying it would take 1 cycle. I know it would take 2, that's not my point, I'm just saying that it should be noted on the instruction summary or somewhere there that some instructions might take 2 cycles under some circumstances (and of course tell and explain those circumstances). Now, If you read the WHOLE datasheet you will know that addwf PCL, F will take 2 cycles, but a quick look must also reveal that... Mauricio Jancic Janso Desarrollos Microchip Consultant Program Member (54) 11-4542-3519 spamBeGoneinfospamBeGonejanso.com.ar http://www.janso.com.ar ____________________________________________

> When the mention the BTFSx the say that it will take 2 cycles > under certain circumstances That's right, but that's due to a very different cause: thik of the skipped instruction executed as a NOP. Any document can be improved. That's why the piclist is a major argument in favour of using PICs :) Wouter van Ooijen -- ------------------------------------------- Van Ooijen Technische Informatica: http://www.voti.nl consultancy, development, PICmicro products docent Hogeschool van Utrecht: http://www.voti.nl/hvu ____________________________________________

> I know a 'call' equals 2 'nop's. what about the 'return'? To check the answers that you've been given, use the Stopwatch function of MPLAB Debugger/Settings to set the frequency then Debugger/Stopwatch Right-click in code to "Set PC At Cursor", double-left-click to make a breakpoint and F9 to run ____________________________________________

Hi. You could also check the thread "'[PIC]: ADDWF PCL,F'" From Jan-2004 in the PIClist archives : http://www.piclist.com/techref/postbot.asp?by=thread&id=%5BPIC%5D%3A+ADDWF+PCL%2CF&tgt=browse (I'm not sure you can see that link directly, you must be a registred user of the PIClist archives to be able to search it...) That thread was about exactly the same thing. Best Regards, Jan-Erik. ____________________________________________

Mauricio Jancic wrote: > That's my point. > When the mention the BTFSx the say that it will take 2 cycles under > certain circumstances, but they not advice that on the other > instructions that might modify the PCL register. I wouldn't really want them to clutter up the description of each instruction with the special case "except when the result is written to PCL, then it takes an extra cycle". This IS said elsewhere in the manual, and should also be obvious from common sense about how the PIC works, which is also in the manual. > Now, If you read the WHOLE datasheet you will know that Yes, there are many useful things one will know after reading the whole datasheet. That's why they wrote the whole data sheet. ***************************************************************** Embed Inc, embedded system specialists in Littleton Massachusetts (978) 742-9014, http://www.embedinc.com ____________________________________________

At 01:20 PM 12/9/2004, Jan-Erik Soderholm wrote: > call wait4cycles ; 4 cycles > goto $+1 ; 2 cycles > nop ; 1 cycle > > >Then put the "wait4cycles" label right before the return >in an *existing* subroutine. No extra code for that. I interpreted the original poster's question as wanting to NOT call a subroutine. I could easily have been wrong . . . dwayne -- Dwayne Reid <TakeThisOuTdwaynerEraseMEspam_OUTplanet.eon.net> Trinity Electronics Systems Ltd Edmonton, AB, CANADA (780) 489-3199 voice (780) 487-6397 fax Celebrating 20 years of Engineering Innovation (1984 - 2004) .-. .-. .-. .-. .-. .-. .-. .-. .-. .- `-' `-' `-' `-' `-' `-' `-' `-' `-' Do NOT send unsolicited commercial email to this email address. This message neither grants consent to receive unsolicited commercial email nor is intended to solicit commercial email. ____________________________________________

>>Yes, there are many useful things one will know after reading >>the whole datasheet. That's why they wrote the whole data sheet. >> Yes... Olin, you are right. Mauricio Jancic Janso Desarrollos Microchip Consultant Program Member (54) 11-4542-3519 RemoveMEinfoTakeThisOuTjanso.com.ar http://www.janso.com.ar ____________________________________________

On Thu, 2004-12-09 at 17:05 -0500, Olin Lathrop wrote: > Mauricio Jancic wrote: > > That's my point. > > When the mention the BTFSx the say that it will take 2 cycles under > > certain circumstances, but they not advice that on the other > > instructions that might modify the PCL register. > > I wouldn't really want them to clutter up the description of each > instruction with the special case "except when the result is written to PCL, > then it takes an extra cycle". This IS said elsewhere in the manual, and > should also be obvious from common sense about how the PIC works, which is > also in the manual. Sorry Olin, no, the chart in question already has a column for "notes", adding a small "3" to that instruction (as has been added on many of the other instructions) would NOT clutter up the chart at all, and would make things much more clear to newer people. Adding a note to each instruction's description WOULD however clutter things up. TTYL ----------------------------- Herbert's PIC Stuff: http://repatch.dyndns.org:8383/pic_stuff/ ____________________________________________

{Quote hidden}>-----Original Message----- >From: piclist-bouncesEraseME.....mit.edu [EraseMEpiclist-bouncesmit.edu] >Sent: 09 December 2004 19:58 >To: Microcontroller discussion list - Public. >Subject: RE: [PIC] instrction cycle > > >On Thu, 2004-12-09 at 15:53 -0300, Mauricio Jancic wrote: >> What about ADDWF PCL, F ?? >> It takes only 1 cicle, the datasheet says... > >But it doesn't, I just sim'd it and it clearly uses two cycles. > >Very interesting, MChip has "note 3" on the instruction set >summary, but doesn't apply it to that instruction. > >On the page before it only mentions if PC is MODIFIED by an >instruction does it take two cycles. > >I've attached the results of sim. > >TTYL Although in this case it is correct, to my mind it takes a leap of faith to implicitly belive the MPLAB simulator results in poorly documented situations like this. It does have a history of small timing inaccuracies. Regards Mike ======================================================================= This e-mail is intended for the person it is addressed to only. The information contained in it may be confidential and/or protected by law. If you are not the intended recipient of this message, you must not make any use of this information, or copy or show it to any person. Please contact us immediately to tell us that you have received this e-mail, and return the original to us. Any use, forwarding, printing or copying of this message is strictly prohibited. No part of this message can be considered a request for goods or services. ======================================================================= ____________________________________________

On Mon, 2004-12-13 at 09:39 +0000, Michael Rigby-Jones wrote: > Although in this case it is correct, to my mind it takes a leap of faith > to implicitly belive the MPLAB simulator results in poorly documented > situations like this. It does have a history of small timing > inaccuracies. I also wouldn't blindly trust MPLABs sim, but as you mention in this case it proved correct. FWIW if MPLAB sim starts to produce "odd" things I usually go to the ICD2, the real chip will behave in the way the real chip will behave! :) TTYL ----------------------------- Herbert's PIC Stuff: http://repatch.dyndns.org:8383/pic_stuff/ ____________________________________________