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'[PIC] hspll mode not assembling correctly'
2005\05\01@221714 by Marcel Duchamp

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I'm having some kind of problem getting the hspll mode to work on a
PIC18F4620.  Checking with a scope on a pin being toggled shows
operation 4 times too slow .... looks like the pll is not on.  The 10MHz
crystal is in fact working at 10MHz.

Yes, I know about power cycling.

Here's what the assembly listing shows:


                00037 ;  __CONFIG _CONFIG1H, _OSC_HS_1H & _OSCS_OFF_1H
300000 F2FF     00038    __CONFIG _CONFIG1H, _OSC_HS_1H & _OSC_HSPLL_1H

The F2 remains the same for either of the two config lines above.  The
correct value for "pll on" is F6 (the next FF shown is for the next
config line, not related to the pll)

So I'm doing something exceptionally stupid or the assembler is having
fun at my expense... any ideas???
Thanks!
MD

2005\05\02@073401 by olin_piclist

face picon face
Marcel Duchamp wrote:
> I'm having some kind of problem getting the hspll mode to work on a
> PIC18F4620.  Checking with a scope on a pin being toggled shows
> operation 4 times too slow .... looks like the pll is not on.  The 10MHz
> crystal is in fact working at 10MHz.

Right.  The PLL doesn't change the frequency the crystal operates at.  It
takes the frequency from the crystal and multiplies it by 4 for internal
use.  You won't see 40MHz on any pin.


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2005\05\02@100339 by Marcel Duchamp

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Olin Lathrop wrote:
> Marcel Duchamp wrote:
>
>> I'm having some kind of problem getting the hspll mode to work on a
>> PIC18F4620.  Checking with a scope on a pin being toggled shows
>> operation 4 times too slow .... looks like the pll is not on.  The 10MHz
>> crystal is in fact working at 10MHz.
>
>
> Right.  The PLL doesn't change the frequency the crystal operates at.  It
> takes the frequency from the crystal and multiplies it by 4 for internal
> use.  You won't see 40MHz on any pin.

Yes, I know that. I wasn't looking for 40MHz on any pin. I'm looking for
 instructions moving along at 10mips; I'm getting 2.5mips.  The correct
value is not being assembled; that is my question. Thus, the pll is
never being commanded to be active.  As mentioned before, the config
value in my program listing is 0xf2; it should be 0xf6.  Again, my
question is why is the assembler generating 0xf2?
MD

2005\05\02@104908 by Wouter van Ooijen

face picon face


{Quote hidden}

> --

2005\05\02@111820 by Marcel Duchamp

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Marcel Duchamp wrote:
As mentioned before, the config
> value in my program listing is 0xf2; it should be 0xf6.  Again, my
> question is why is the assembler generating 0xf2?
> MD
>

Further investigation has found that the correct code is assembled if
this line is used:

       __CONFIG 300001, 0x00f6

instead of this:

       __CONFIG _CONFIG1H, _OSC_HS_1H & _OSC_HSPLL_1H

The pll does turn on and the expected 10mip performance does happen. I
still do not understand why the usual config statements are not
assembling correctly... and yes, I have this at the top:

       LIST P=18F4620                ;directive to define processor
       #include <P18F4620.INC>        ;processor specific variable definitions

???
MD

2005\05\02@114302 by Jason Harper

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Marcel Duchamp wrote:
>         __CONFIG _CONFIG1H, _OSC_HS_1H & _OSC_HSPLL_1H

You're supplying two different values for the oscillator configuration!
Get rid of the HS value if you want to use HSPLL.
       Jason Harper

2005\05\02@114417 by Jan-Erik Soderholm

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Marcel Duchamp wrote :

> Further investigation has found that the correct code is assembled if
> this line is used:
>
>        __CONFIG 300001, 0x00f6
>
> instead of this:
>
>        __CONFIG _CONFIG1H, _OSC_HS_1H & _OSC_HSPLL_1H
>
> The pll does turn on and the expected 10mip performance does
> happen.

You should use "_OSC_HS_1H"    **OR**    "_OSC_HSPLL_1H".
Not both at the same time...

They are two different osc settings...

Jan-Erik.



2005\05\02@120330 by Marcel Duchamp

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Jason and Jan-Erik wrote:
> You should use "_OSC_HS_1H"    **OR**    "_OSC_HSPLL_1H".
> Not both at the same time...
>

Ooops.
Thanks! I knew I was doing something wrong... looking back at it, of
course it makes perfect sense now.
Thanks for the right answer.
MD

2005\05\02@183317 by Bob Ammerman

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Don't use both _OSC_HS_1H and _OSC_HSPLL_1H

Just use: _OSC_HSPLL_1H

Bob Ammerman
RAm Systems

----- Original Message -----
From: "Marcel Duchamp" <marcel.duchampspamKILLspamsbcglobal.net>
To: "Microcontroller discussion list - Public." <.....piclistKILLspamspam.....mit.edu>
Sent: Monday, May 02, 2005 11:16 AM
Subject: Re: [PIC] hspll mode not assembling correctly


{Quote hidden}

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