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'[PIC] dsPIC details'
2009\06\25@180402 by solarwind

picon face
Section 2.1 of the dsPIC3FJ128GP802 shows a schematic of a minimal set
of connections. For your viewing convenience, I have provided a link
to the picture below:

http://img150.imageshack.us/img150/5641/mincon.png

1. There is a 10 ohm resistor from AVDD to VDD. What is the idea behind this?

2. Could someone please explain what the circuitry near the MCLR pin
is doing? Is it just a pullup on the MCLR with a decoupling cap? Or is
there something else going on?

3. The dsPIC has an internal voltage regulator that regulates voltage
to its core (I believe). What kind of regulator is it? (ex. linear,
charge pump based, so on)

4. I'm guessing that the decoupling caps act as mufflers for
noise/spikes/dips and compensate for abrupt voltage changes. In that
case, I can see why they are placed in (parallel?) with the power
lines. However, there is a cap placed in series with the VCAP/VDDCORE
line. How does this cap behave? What does it do?

-- [ solarwind ] -- http://solar-blogg.blogspot.com/

2009\06\25@184517 by peter green

flavicon
face
solarwind wrote:
> Section 2.1 of the dsPIC3FJ128GP802 shows a schematic of a minimal set
> of connections. For your viewing convenience, I have provided a link
> to the picture below:
>
> http://img150.imageshack.us/img150/5641/mincon.png
>
> 1. There is a 10 ohm resistor from AVDD to VDD. What is the idea behind this?
>  
Most likely to act in combination with the decoupling capacitor as a
power supply filter for the analog supply. It can probablly be replaced
with a wire if you aren't too concerned about ADC accuracy.

> 2. Could someone please explain what the circuitry near the MCLR pin
> is doing? Is it just a pullup on the MCLR with a decoupling cap? Or is
> there something else going on?
>  
It looks to me like a circuit designed to delay the rise of MCLR to hold
the chip in reset while the power supply comes up and stabalises. Note
that on the other side of that page they reccomend that you make the
capacitor disconnectable and disconnect it for programming/debug purposes.

> 3. The dsPIC has an internal voltage regulator that regulates voltage
> to its core (I believe). What kind of regulator is it? (ex. linear,
> charge pump based, so on)
>  
I can't seem to find a reference in the datasheet but given that the
only external component is a capacitor on it's output it is almost
certainly a linear regulator.
> 4. I'm guessing that the decoupling caps act as mufflers for
> noise/spikes/dips and compensate for abrupt voltage changes.
Their main purpose is to stop current spikes (which are a fact of life
with cmos logic) turning into voltage spikes/dips
> In that
> case, I can see why they are placed in (parallel?) with the power
> lines. However, there is a cap placed in series with the VCAP/VDDCORE
> line. How does this cap behave? What does it do?
>  
It is in paralell with the regulator output. The regulator is connected
internally to the core but you have to provide a decoupling capacitor to
ground externally because large capacitors are very difficult/expensive
to integrate in an IC.


2009\06\25@184622 by olin piclist

face picon face
solarwind wrote:
> http://img150.imageshack.us/img150/5641/mincon.png
>
> 1. There is a 10 ohm resistor from AVDD to VDD. What is the idea
> behind this?

Low pass filtering.

> 2. Could someone please explain what the circuitry near the MCLR pin
> is doing? Is it just a pullup on the MCLR with a decoupling cap? Or is
> there something else going on?

Probably to wait to assert MCLR until a little while after the power has
come up.  The series resistor may be to isolate the programmer from the cap.

> 3. The dsPIC has an internal voltage regulator that regulates voltage
> to its core (I believe). What kind of regulator is it? (ex. linear,
> charge pump based, so on)

Whatever the datasheet says it is.

> 4. I'm guessing that the decoupling caps act as mufflers for
> noise/spikes/dips and compensate for abrupt voltage changes.

No need to guess.  I'm sure there is lots of stuff out there on "decoupling"
or "bypass" caps.

> In that
> case, I can see why they are placed in (parallel?) with the power
> lines. However, there is a cap placed in series with the VCAP/VDDCORE
> line. How does this cap behave? What does it do?

Vddcore is the output of the internal core voltage regulator.  The cap is
between this power voltage and ground.  It absorbs high frequency current
spikes and may also be necessary for the stability of the internal Vddcore
regulator.


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Embed Inc, Littleton Massachusetts, http://www.embedinc.com/products
(978) 742-9014.  Gold level PIC consultants since 2000.

2009\06\25@204320 by solarwind

picon face
On Thu, Jun 25, 2009 at 11:45 PM, peter green<spam_OUTplugwashTakeThisOuTspamp10link.net> wrote:
{Quote hidden}

Thank you for that detailed response to my lengthy question. I
understand the circuit a lot better now. I just hooked up everything
with a little modification and it all seems to be working as expected.
I just need to write some code and load it up now!

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