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'[PIC] Unclear about POSTINCn when indirect address'
2007\07\12@074830 by Matthew Rhys-Roberts

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Hi all,

This is my first post here, so I hope this makes sense.

Please could anyone confirm whether I've understood how POSTINC works
when using indirect addressing. Here's a snippet of someone's
pre-written code that I'm trying to figure out, with my comments alongside:

   LFSR    FSR0,0x100       ; load FSR with address 100h
   MOVLW   A'2'             ; put ascii character "2" into W
   MOVWF   POSTINC0,A       ; store W at address 100h  ???????
   MOVF    lowbyte,W,A      ; get local variable 'lowbyte' into W
   MOVWF   POSTINC0,A       ; store it at address 101h ???????

As far as I can see, we load the FSR with address 100h, then the first
MOVWF stores W at 100h, the second MOVWF stores W at 101h, etc.

Am I right?

Many thanks,

Matt Rhys-Roberts
N. Wales, UK

2007\07\12@082448 by Dario Greggio

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Matthew Rhys-Roberts wrote:

> As far as I can see, we load the FSR with address 100h, then the first
> MOVWF stores W at 100h, the second MOVWF stores W at 101h, etc.
>
> Am I right?

Yes, this makes all sense to me :)

PS: Welcome :)

--
Ciao, Dario
--
ADPM Synthesis sas - Torino
--
http://www.adpm.tk

2007\07\12@082911 by Jan-Erik Soderholm

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Matthew Rhys-Roberts wrote:
> Hi all,
>
> This is my first post here, so I hope this makes sense.
>
> Please could anyone confirm whether I've understood how POSTINC works
> when using indirect addressing. Here's a snippet of someone's
> pre-written code that I'm trying to figure out, with my comments alongside:
>
>     LFSR    FSR0,0x100       ; load FSR with address 100h
>     MOVLW   A'2'             ; put ascii character "2" into W
>     MOVWF   POSTINC0,A       ; store W at address 100h  ???????
>     MOVF    lowbyte,W,A      ; get local variable 'lowbyte' into W
>     MOVWF   POSTINC0,A       ; store it at address 101h ???????
>
> As far as I can see, we load the FSR with address 100h, then the first
> MOVWF stores W at 100h, the second MOVWF stores W at 101h, etc.
>
> Am I right?

Yes, just as the datasheet says... :-)

What was unclear ?

Jan-Erik.

>
> Many thanks,
>
> Matt Rhys-Roberts
> N. Wales, UK

2007\07\12@082940 by Jinx

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> As far as I can see, we load the FSR with address 100h, then the
> first MOVWF stores W at 100h, the second MOVWF stores W
> at 101h, etc.
>
> Am I right?

Hi Matt, welcome. Yes, POSTINC0 performs INCF FSR0L and
increments FSR0H if necessary

For the 18F

. Do nothing to FSRn after an indirect access - INDFn
. Auto-decrement FSRn after an indirect access - POSTDECn
. Auto-increment FSRn after an indirect access - POSTINCn
. Auto-increment FSRn before an indirect access - PREINCn
. Use the value in the WREG register as an offset to FSRn. Do
not modify the value of the WREG or the FSRn register after an
indirect access (no change) - PLUSWn

3 FSRs and the above is why I prefer the 18F for anything
involving data manipulation, editing or searching RAM tables
etc. Some code I recently ported over from the 16F was made
so much more efficient, readable and easily modified by not
needing to clutter up the place with scratch RAM and data-
swapping variables

2007\07\12@084353 by Jinx

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Seeing as FSRs are in the spotlight, when needing to set an
FSR to a 12-bit variable name, my first instinct was to write
a macro (eg this for FSR0)

setfsr0  macro   file
        movlw   low(file)
        movwf   fsr0l
        movlw   high(file)
        movwf   fsr0h
        endm

and use it thus

rec_bytes = 0x280 ;address of receive buffer RAM

 setfsr0 rec_bytes ;set FSR0 to receive buffer

I haven't really looked back or thought about what I did, and it
works OK, but is that the only way to do it within MPLAB ? If
there is and it saves a little code space that would be just peachy

*********************

BTW Matt, I wrote

POSTINC0 performs INCF FSR0L and increments FSR0H if
necessary

If you look at the disassembly of a POSTINC directive you'll see
something like

MOVWF POSTINC0,  ACCESS

not INCF FSR0 commands as such, but it does the job

2007\07\12@085105 by Dario Greggio

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Jinx wrote:

> Seeing as FSRs are in the spotlight, when needing to set an [...]

Hmm, am I wrong or LFSR nelongs to Extended Instruction Set?
Me too, have never used it (rather Jinx approach)

2007\07\12@090524 by Jinx

face picon face
> Seeing as FSRs are in the spotlight, when needing to set an
> FSR to a 12-bit variable name, my first instinct was to write
> a macro (eg this for FSR0)

Sorry, disregard. Was thinking of another problem that popped
up once

2007\07\12@091029 by Matthew Rhys-Roberts

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Ok, thanks very much, glad I've understood POSTINC.

Two more questions:

1) Therefore, if I were to use POSTDEC in the example below, would it
store the first value at 100h, the next at FFh, FEh, etc?
2) And if I used PREINC, would the first value be stored at 101h, then
102h, 103h etc?

Thanks
Matt

>     LFSR    FSR0,0x100       ; load FSR with address 100h
>     MOVLW   A'2'             ; put ascii character "2" into W
>     MOVWF   POSTINC0,A       ; store W at address 100h  ???????
>     MOVF    lowbyte,W,A      ; get local variable 'lowbyte' into W
>     MOVWF   POSTINC0,A       ; store it at address 101h ???????

2007\07\12@091335 by Jinx

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> Hmm, am I wrong or LFSR nelongs to Extended Instruction Set?

LFSR is a basic legitimate instruction for all 18F (so I believe). The
EIS is

ADDFSR
ADDULNK
CALLW
MOVSF
MOVSS
PUSHL
SUBFSR
SUBULNK

POSTINC etc are SFRs that must have a little associated logic to
do the post/pre + and - to FSR

2007\07\12@091932 by Dario Greggio

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Jinx wrote:

>>Hmm, am I wrong or LFSR nelongs to Extended Instruction Set?
>
> LFSR is a basic legitimate instruction for all 18F (so I believe). The
> EIS is
>
> ADDFSR
[...]

Thank you Jinx, I was mislead by your previous email :))
and wrote before your further email.

I'm not using ASM on 18F that much, so thanks for clarifying

--
Ciao, Dario

2007\07\12@092819 by Matthew Rhys-Roberts

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Thanks Jinx, that clears things up nicely.
Matt

Jinx wrote:
{Quote hidden}

2007\07\12@102457 by Nicola Perotto

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A very good thing for learning is the MPLAB SIM: you can find it in the
Debugger/Select tool menu of MPLAB IDE.
Thake a look!
       Nic

Matthew Rhys-Roberts wrote:
{Quote hidden}

2007\07\12@194557 by Jinx

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> A very good thing for learning is the MPLAB SIM: you can
> find it in the Debugger/Select tool menu of MPLAB IDE

Under 'View' you'll find File Registers, which displays RAM
and Watch, which lets you see the contents of registers (both
RAM and SFRs), by name and format, as code is executed.
Which can be Run or Single Step. 'Debugger' has Stopwatch
to measure execution time

Help/Topics/MPLAB IDE



2007\07\12@213827 by Jinx

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> A very good thing for learning is the MPLAB SIM: you can find
> it in the Debugger/Select tool menu of MPLAB IDE

I made this simple sniffer to look at RAM whilst the hardware
is running. Doesn't do SFRs but often one can deduce which
SFR caused RAM to go bad. Found it extremely helpful being
able to see what's actually going on in memory

http://www.piclist.com/techref/piclist/jinxlcdregmon.htm

The 2520 was used because it was a spare Microchip sample
and had ample RAM for the time (0x600). Any PIC can be
used as the receiver (but you may as well use a fast big 'un with
plenty of RAM and I/O). For a current project using the 4550,
which has 0x800 of RAM, I'll have to upgrade to a 2550 (also
0x800 RAM). Another sample, bless 'em ;-) Also will add Bank
Select push buttons (+/- 0x100) in addition to the 0x08 up/down

Note -

Not sure how, but the code I gave to James is not what is being
used. Must have been an early draft. Please amend the bit-bang
receive routine to this - the count length is +1 and the final shift is
gone. Apologies. I'll post the correct asm to James. There are
plenty of ways this code can be modified to suit individual cases

reset_c  mov     0x08,cnt1    ;bit counter
        clrf    temp1

chwait   btfss   bbclk        ;wait for bbclk to go high
        bra     chwait
        nop
        nop
        nop
        nop
clwait   btfsc   bbclk        ;data valid when clk goes low
        bra     clwait
        nop
        nop
        nop
        nop

        bsf     temp1,0      ;data buffer
        btfss   bbdata
        bcf     temp1,0

        dcfsnz  cnt1         ;bit counter
        bra     store

        rlncf   temp1        ;buffer
        bra     chwait       ;get next bit

store    movff   temp1,postinc0 ;copy buffer to RAM
        incf    temp
        movlw   0xf0         ;exit after receiving 0xf0 bytes
        xorwf   temp,w
        skpz
        bra     reset_c

************

Here's an example send routine. The receiver is running flat knacker
(40MHz). A fast-running sender may need a few NOPs to allow the
receiver to pick up reliably

;=================================
;        Send data to sniffer PIC
;=================================

#define  bbdata   latb,6      ;bit-bang data
#define  bbclk    latb,7      ;bit-bang clock

pic2pic  lfsr    fsr0,0x0000 ;18F1320 Bank1 RAM

d_loop   movlw   0x08        ;bit count
        movwf   temp0
        movff   indf0,temp1 ;get byte for transfer
        call    send_d
        incfsz  fsr0l       ;loop to 0x0100
        bra     d_loop
        return         ;all bytes sent, exit

send_d   bsf     bbclk       ;clock high
        btfss   temp1,7     ;test, set data line = data bit
        bra     bclr
        bsf     bbdata      ;bit is 1
        nop
        nop
        bra     rot_d       ;next bit

bclr     bcf     bbdata      ;bit is 0
        nop
        nop

rot_d    bcf     bbclk       ;clock low
        nop
        nop
        nop
        nop
        rlncf   temp1       ;next bit into temp1,7
        decfsz  temp0       ;bit count
        bra     send_d
        return              ;byte done

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