Post by thread:[PIC] Re: Reading IC16F877A AN0 and AN1

On 7/23/05, Augusto Yipmantin <spam_OUTaugustoyTakeThisOuTcentaurocomunicaciones.com> wrote: > Hi all, > > I have a circuit that I want to use with a pic16f877a. Two 5K > potentiometers are connected to the pins AN0 and AN1. The program that I > am using reads each pin and shows the value of each pin in an LCD. > What I can see is a little variation after the value is readed, usually > the potentiometer stills in the same position most time. > But, the LCD shows me values one to two up or one to two down from the > center value readed. > It is possible to change something to get a more stable readout? > Maybe I have to use a more precise potentiometer? Not the potmeter is the problem but how much noise there is on the supply voltage. I'm expecting you've wired the potentiometer as a divizor with the center pin (wiper) to the analogic imputs. Check out the noise on the VCC using a scope or a DMM with high resolution and see how many readouts can you see on the last digit (which is moving around a center value up and down). With a scope will be better, but doubts you have one. Filter the reference voltage in the potentiometer input using an RC with a time delay of 10-100mS. A 47nF to 100nF on the analogic pins to ground, may help too but decrease the time response of the circuit. Wrong wired grounds also alter the results on AD. To small Tad (aquisition time) or messy readings on bank1 could gave you the same situation. dig on, Vasile

Dear Vasile, You are right; the potentiometer is wired as a divisor with the center pin wired to the AN0 and AN1 pins (two potentiometers I am using, one for each pin). The circuit is mounted in a proto board and the supply is a 12V@8Ah battery, so the origin of the noise maybe will be from the wiring. I will check the reference voltage. Regards, Augusto Vasile wrote: Not the potmeter is the problem but how much noise there is on the supply voltage. I'm expecting you've wired the potentiometer as a divizor with the center pin (wiper) to the analogic imputs. Check out the noise on the VCC using a scope or a DMM with high resolution and see how many readouts can you see on the last digit (which is moving around a center value up and down). With a scope will be better, but doubts you have one. Filter the reference voltage in the potentiometer input using an RC with a time delay of 10-100mS. A 47nF to 100nF on the analogic pins to ground, may help too but decrease the time response of the circuit. Wrong wired grounds also alter the results on AD. To small Tad (aquisition time) or messy readings on bank1 could gave you the same situation. dig on, Vasile

On Saturday 23 July 2005 09:10 am, Vasile Surducan scribbled: > ... > Filter the reference voltage in the potentiometer input using an RC > with a time delay of 10-100mS. A 47nF to 100nF on the analogic pins to > ground, may help too but decrease the time response of the circuit. > ... I would also think that the Vdd to the chip should be as close to the pot's reference voltage (or a ratio thereof), so that the A/d input and the A/d reference inside the PIC are proportional. Perhaps try using the same reference voltage at the pot to drive the external Vref+ at the PIC. Cheers, -Neil.