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'[PIC] Re: Phase of internal TMR0 clocking [OT]'
Yeah, the picture looks mystical ;) but explains nothing.
It sounds like we have done in this way so please use it
with no any questions about reasonability ;)
Probably I should address this question to some tech guy
in Microchip ( maybe some of them are presented here ? )
> > Can you explain what do you mean getting back in sync with internal clock > > Situation is following: prescaler=1, internal osc/4 is used.
> If you look at the data sheet and the TMR0 block diagram, you will see a
> SYNC circuit following the PSA MUX. The data sheet mentions a (2 cycle
> delay) under the SYNC block. Whether this is coincidence or related, I
> don't know.
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