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'[PIC] Possible PLL problem with 18f452?'
2004\03\04@205038 by John Spiliotopoulos

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Hi guys!

I've been monitoring the list every now and then (it is difficult to keep up) and I must say it's been the ultimate resource of ideas and debugging techniches for me. But this time I have a problem I can't figure out!

I'm experiencing strange behaviour with the 452 and the PLL enabled:

I have Timer0 creating a High Int every about 400us and in the ISR I load data to 4 HC373 latches (each one is selected by the output of a HC238 decoder), then point to 1 of 16 outputs via a HC154 and then exit the ISR (data latched is different each time).

When I am using a 10MHz crystal with the PLL enabled (10Mhz clock) the code runs for about 2-3 seconds then hangs inside the ISR routine (I know it is in the ISR because I have a LED turned on when inside the ISR for debugging reasons). Even with a 4MHz crystal (4MHz clock) I get the same behaviour (without changing anything else the code).

But, when I disable the PLL the code runs as expected without any lockup, even with a 20MHz crystal (that gives 5MHz clock, bigger than the 4MHz tested with the PLL).

The date code of the chip is 0348 0J8, so it should be a C0 silicon revision, which is also what my programmer thinks because it reports rev 0x07.
There is nothing in the errata for this (or previous) silicon revisions regarding the PLL. Am I doing something wrong?

Thank you in advance for your answer and excuse my English!

John Spiliotopoulos / Greece

Below is the ISR code:
; LatchEn  is PORTB, RC4 when high disables HC154 and enables HC238&HC373
; DataPort is PORTD
; DecPort is PORTB and pins<3:0> connect to the inputs of HC154 and <1:0> to HC238
; Also FSR0H is always set to 01 where a 4lines x 16rows data table exists

HighInt:
 bsf  LATA, RA0   ; Light up RA0 to indicate mode
 btfsc CurDisplayRow, 4 ; Check if CurDisplayRow overflowed to 17
 clrf CurDisplayRow  ; If yes, set it to 0

 bsf  LatchEn    ; Set LatchEnable
 ; Routine to load buffers with data
 bcf  DecPort, 0   ; Select buffer 00
 bcf  DecPort, 1   ; Select buffer 00
 movff CurDisplayRow, FSR0L; Get current value of DisplayRow to FSR table
 movff INDF0, DataPort  ; Send data to port
 bsf  DecPort, 0   ; Select buffer 01
 bsf  FSR0L, 4   ; And also appropriate register
 movff INDF0, DataPort  ; Send data to port
 bsf  DecPort, 1   ; Select buffer 11
 bsf  FSR0L, 5   ; And also appropriate register
 movff INDF0, DataPort  ; Send data to port
 bcf  DecPort, 0   ; Select buffer 10
 bcf  FSR0L, 4   ; And also appropriate register
 movff INDF0, DataPort  ; Send data to port

 ; This routine is needed to maintain the data on DecPort<7:4>
 bcf  LatchEn    ; Disable LatchEnable, displays Data
 movlw b'11100000'   ; Value to mask
 andwf DecLatch, w   ; AND it with current output
 xorwf CurDisplayRow, w ; XOR it with DisplayRow value
 movwf DecPort    ; Get previous value of w to DecPort
 incf CurDisplayRow, f ; Increase CurDisplayRow to point to next Row
 bcf  LATA, RA0   ; Exiting of DisplayUpdate mode, clear indicator
 bcf  INTCON, TMR0IF  ; Clear INT flag
 retfie FAST    ; Return FAST

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2004\03\05@015150 by Wouter van Ooijen

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> I'm experiencing strange behaviour with the 452 and the PLL enabled:

You do know that the PLL on/off setting takes its (new) effect only
after a power down - power up?

Wouter van Ooijen

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Van Ooijen Technische Informatica: http://www.voti.nl
consultancy, development, PICmicro products

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2004\03\05@084846 by John Spiliotopoulos

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>> I'm experiencing strange behaviour with the 452 and the PLL enabled:

>You do know that the PLL on/off setting takes its (new) effect only
after a power down - power up?

Yes I do, I found out the hard way the first time I tried to use it :-)

Each time I enable or disable the PLL I remove power and then reaply...

Also I discovered another problem I can't figure out. The following code:

 movlw 'T'
 movwf TXREG
a1:  btfss PIR1, TXIF
 goto a1
 movlw 'e'
 movwf TXREG
b1:  btfss PIR1, TXIF
 goto b1
 movlw 's'
 movwf TXREG
c1:  btfss PIR1, TXIF
 goto c1
 movlw 't'
 movwf TXREG
d1:  btfss PIR1, TXIF
 goto d1
 movlw '-'
 movwf TXREG
e1:  btfss PIR1, TXIF
 goto e1

That should give "Test-" as a UART output gives only "Ts-"! Baud rate is 19.2Kbps. Even if I put it at a continous loop it keeps displaying "Ts-Ts-Ts-Ts-". The same code with a 877 in place of the 452 works fine.

Could it be that my micro is damaged? How could that happen?

John Spiliotopoulos/Greece

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2004\03\05@090056 by Joe Jansen/TECH/HQ/KEMET/US

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Hey!  I can finally contribute!

From the datasheet (I am looking at the sheet for the 18f242 that I just
finished the same type of project for):

<quote>
NOTE:  TXIF is not cleared immediately upon loading data into the transmit
buffer TXREG.  The flag bit becomes valid in the second instruction cycle
following the load instruction.
</quote>

therefore, your test at a1, which is the first instruction following the
load, is testing TXIF before it gets updated from loading TXREG.


Hope this helps!

--Joe Jansen




pic microcontroller discussion list <PICLISTspamKILLspamMITVMA.MIT.EDU> wrote on
03/05/2004 08:46:19 AM:

> >> I'm experiencing strange behaviour with the 452 and the PLL enabled:
>
> >You do know that the PLL on/off setting takes its (new) effect only
> after a power down - power up?
>
> Yes I do, I found out the hard way the first time I tried to use it :-)
>
> Each time I enable or disable the PLL I remove power and then reaply...
>
> Also I discovered another problem I can't figure out. The following
code:
{Quote hidden}

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2004\03\05@112332 by Brian Clewer

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John wrote:

> Hi guys!
>
> I've been monitoring the list every now and then (it is difficult
> to keep up) and I must say it's been the ultimate resource of
> ideas and debugging techniches for me. But this time I have a
> problem I can't figure out!
>
> I'm experiencing strange behaviour with the 452 and the PLL enabled:
>

Are you using the regulatory 100nF caps close to the power pins?
Are you using a small cap from the Mclr down to ground with a pullup on the
pin?

You might find it's noise on the supply / Mclr and the PLL draws that extra
bit of current to tip it over the edge.

Brian.

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2004\03\05@155714 by Omega Software

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>Are you using a small cap from the Mclr down to ground with a pullup on the
>pin?

Wouldn't it be easier to just enable the POR (Power On Reset) feature (which
the mentioned PIC18F452 has)?

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2004\03\06@035844 by Brian Clewer

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Omega wrote:

>
> >Are you using a small cap from the Mclr down to ground with a
> pullup on the
> >pin?
>
> Wouldn't it be easier to just enable the POR (Power On Reset)
> feature (which
> the mentioned PIC18F452 has)?

I see where you are coming from, but what I actually meant here was to
produce a passive low pass filter to reduce any noise that might be present
on the Mclr pin.  It wasn't intended as a POR alternative.

Brian.

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