Post by thread:[PIC] PWM as a switch mode

> Has anyone worked on a system using PWM to create a SMPSU where the > PIC/MCU supply is being generated from the PWM. I know this will need a > bootstrap mechanism and I guess that is what I am most interested. You need to be more specific about - available supply voltage and - PIC minimum startup voltage. Part number would help muchly. - acceptable startup conditions / triggers. For example, if startup is a user switch action you can drive a voltage doubler with a single switch action. The excessively enthused can manage double-double, with diode losses with a push and release two part action with an eg DPDT switch. If have 2 cell supply it is much easier than 1 cell supply. etc eg With a simple voltage double Cpump will charge to Vbat - Vd where Vd = a diode drop. Switch action produces Vbat + (Vbat-Vd) - Vd = 2Vbat -2 Vd. You can remove 1 x Vd loss by resistor charging the cap originally and assuming that back flow during pumping is small. You can also "get synchronous" and eliminate Vd drops. Fron 2 (Vb-Vd) and one cell and say Vd = 0.4 then if Vbat = low = 1V you get 1.2V with 2 diodes, 1.6V with one diode and 2V with no diodes. Not too marvellous except for 1.8V parts. If Vbat is 2V min you get 3.2V, 3.6V, 4V respectively = good/better/best. If you ring an inductor yiou can get almost any voltage you want. Extra points for ringing inductor which is subsequently used by PIC. You can get 1 cell to X Volt smps IC's for < 10 cents in Asia. These can make the task MUCH simpler (but less fun) More details please. Russell McMahon Russel

Dear Veronica, At 01.33 2012.06.12, you wrote: >Hi all > >Has anyone worked on a system using PWM to create a SMPSU where the >PIC/MCU supply is being generated from the PWM. I know this will need >a bootstrap mechanism and I guess that is what I am most interested. Yes, in my buck controller the PNP switch is driven by a NPN transistor, whose base is pulled up. The Vreg of the MPU is after this PNP high switch. When power arrives, the PNP high side switch is not fully saturated but lets nice electrons pass, thanks to the pullup on the NPN transistor that drives the PNP base, and power leaks into the VReg and consequently the MPU, which is held in reset until power is good ( = voltage at VReg is within 98% or so of stable output voltage). At this point the reset line is not held down anymore, the MPU gets out of reset, and drives the NPN transistor base actively, 0 or 1, not tristate anymore, being thus able to saturate the PNP transistor or switch it off completely. It works, and the oscilloscope shows that it even works very well. I can give more details if you want, e.g. it's even a high tension power input (400V). NPN collector into PNP base (through a resistor of course), NPN base pulled up via high value resistor to PNP emitter. Not exactly, as the pullup resistor doesn't go into NPN base but into MPU pin, and the latter goes, through a low value resistor, into NPN base. The MPU pin never seen high voltage, as it's clamped by the NPN base, through the low value resistor. Currents into base, out of pin, etc.. are all much within absolute max values, always, when MPU I/O pin is tristated, as well as when it is actively driven to 0 or 1. One difference with your design is that I don't use PWM, but I drive the NPN base directly via an algorithm (my MPU is doing much more than the buck part, it's a complex/articulated system), but it doesn't change the substance, as after reset you can enable the PWM module instead of bit banging the I/O pin like I do. >Thanks I'm really very glad if I had a chance to help you. Cheers, Mario > >Veronica > > >

Dear Mario I wonder if I could cross check my numbers with you. It has taken me a whir to get back to doing this mainly because when I was initially asking it was just an idea and now it is to be designed. So this is a buck regulator running from a 4 cell battery pack, so I am assuming I have a min voltage of 5v. When the unit is on charger, the input will be nearer 7 to 8 volts. My PNP is 500mA max, hfs of 100 min. The NPNP is 600mA with a min hfs of 100. These choices were cost driven within the required specs. I get a PNP base resistor of about 700 ohms, NPN base resistor of 10K (lower than the limit) and a bleed resistor of 380M to give me a bootstrap current of 100uA for a 31Khz LF-INT PIC oscillator. I could up the boot strap to current to 700uA and start with a 1Mhz HF-INT osc. When I got 380M I became doubtful of my figures and wanted to cross check with you. Thanks Veronica On 2012-06-11, at 11:28 PM, Electron <.....electron2k4KILLspam@spam@infinito.it> wrote: {Quote hidden}> > Dear Veronica, > > > At 01.33 2012.06.12, you wrote: >> Hi all >> >> Has anyone worked on a system using PWM to create a SMPSU where the >> PIC/MCU supply is being generated from the PWM. I know this will need >> a bootstrap mechanism and I guess that is what I am most interested. > > Yes, in my buck controller the PNP switch is driven by a NPN transistor, > whose base is pulled up. The Vreg of the MPU is after this PNP high switch. > > When power arrives, the PNP high side switch is not fully saturated but > lets nice electrons pass, thanks to the pullup on the NPN transistor that > drives the PNP base, and power leaks into the VReg and consequently the MPU, > which is held in reset until power is good ( = voltage at VReg is within > 98% or so of stable output voltage). > > At this point the reset line is not held down anymore, the MPU gets out of > reset, and drives the NPN transistor base actively, 0 or 1, not tristate > anymore, being thus able to saturate the PNP transistor or switch it off > completely. > > It works, and the oscilloscope shows that it even works very well. > > I can give more details if you want, e.g. it's even a high tension power > input (400V). NPN collector into PNP base (through a resistor of course), > NPN base pulled up via high value resistor to PNP emitter. Not exactly, > as the pullup resistor doesn't go into NPN base but into MPU pin, and > the latter goes, through a low value resistor, into NPN base. The MPU pin > never seen high voltage, as it's clamped by the NPN base, through the low > value resistor. Currents into base, out of pin, etc.. are all much within > absolute max values, always, when MPU I/O pin is tristated, as well as when > it is actively driven to 0 or 1. > > One difference with your design is that I don't use PWM, but I drive the > NPN base directly via an algorithm (my MPU is doing much more than the > buck part, it's a complex/articulated system), but it doesn't change the > substance, as after reset you can enable the PWM module instead of bit > banging the I/O pin like I do. > > >> Thanks > > I'm really very glad if I had a chance to help you. > > Cheers, > Mario > > >> >> Veronica >> >> >> --

I'm not Mario :-). Bleed resistor is notionally vaguely correct but impractical and unnecessarily high - any leakage at PIC pin will kill the system by eating the 10 or so Nanoamps that you make available to it. Main issue is, if you have a high startup current then Vout may climb too high before loop starts. If Rbleed = 10M,Vin max = 8V. IRbleed ~= (8-0.6)/10M = 1 uA say. I NPN =~~~ 100 uA. I_PNP boot ~~~= 10 mA. Cout and load on Vout will limit rise time. Using Cout for rise time limiting and 3V as max allowed uncontrolled rise, you'll get ABOUT 3 ms/ uF of Cout. So 10 uF = 30 mS. 100 uF = 300 mS. A safish solution is to add a NPN clamp to the NPN base such that if Vout rises above V_too_high then it turns on clamp and turns off main NPN. You then have a smps in its own right. You can set trip level with a zener or resistor divider to somewhat above the uP will control it at. Hey - we just rererere-invented 'my' GSR switching regulator :-) Mario's system uses (it seems) very high Vin (hundreds of Volts).. You do not say what Vout is but I assume 3V3. With 4 cells your Vin_min is say 4V, not 5V. Vmin for Alkaline, NiCd, NimH is all about 1 V/cell. NPN need not be high current. PNP needs to match your Iout need. You can use lower Beta if desired. I've found BC337.BC327 = BC807/BC817 = about as cheap as any and better spec than most for glue use. You may want to use lower resistor values in drive to transistors tp get better switching speeds. You may find a speedup cap (start with 0.001 uF) across base drive R's improves waveforms. Russell On 23 February 2013 13:27, Veronica Merryfield <veronica.merryfieldKILLspamgmail.com> wrote: {Quote hidden}> Dear Mario > > I wonder if I could cross check my numbers with you. It has taken me a whir to get back to doing this mainly because when I was initially asking it was just an idea and now it is to be designed. > > So this is a buck regulator running from a 4 cell battery pack, so I am assuming I have a min voltage of 5v. When the unit is on charger, the input will be nearer 7 to 8 volts. > > My PNP is 500mA max, hfs of 100 min. The NPNP is 600mA with a min hfs of 100. These choices were cost driven within the required specs. > > I get a PNP base resistor of about 700 ohms, NPN base resistor of 10K (lower than the limit) and a bleed resistor of 380M to give me a bootstrap current of 100uA for a 31Khz LF-INT PIC oscillator. I could up the boot strap to current to 700uA and start with a 1Mhz HF-INT osc. > > When I got 380M I became doubtful of my figures and wanted to cross check with you. > > Thanks > > Veronica > > > On 2012-06-11, at 11:28 PM, Electron <.....electron2k4KILLspam.....infinito.it> wrote: > >> >> Dear Veronica, >> >> >> At 01.33 2012.06.12, you wrote: >>> Hi all >>> >>> Has anyone worked on a system using PWM to create a SMPSU where the >>> PIC/MCU supply is being generated from the PWM. I know this will need >>> a bootstrap mechanism and I guess that is what I am most interested. >> >> Yes, in my buck controller the PNP switch is driven by a NPN transistor, >> whose base is pulled up. The Vreg of the MPU is after this PNP high switch. >> >> When power arrives, the PNP high side switch is not fully saturated but >> lets nice electrons pass, thanks to the pullup on the NPN transistor that >> drives the PNP base, and power leaks into the VReg and consequently the MPU, >> which is held in reset until power is good ( = voltage at VReg is within >> 98% or so of stable output voltage). >> >> At this point the reset line is not held down anymore, the MPU gets out of >> reset, and drives the NPN transistor base actively, 0 or 1, not tristate >> anymore, being thus able to saturate the PNP transistor or switch it off >> completely. >> >> It works, and the oscilloscope shows that it even works very well. >> >> I can give more details if you want, e.g. it's even a high tension power >> input (400V). NPN collector into PNP base (through a resistor of course), >> NPN base pulled up via high value resistor to PNP emitter. Not exactly, >> as the pullup resistor doesn't go into NPN base but into MPU pin, and >> the latter goes, through a low value resistor, into NPN base. The MPU pin >> never seen high voltage, as it's clamped by the NPN base, through the low >> value resistor. Currents into base, out of pin, etc.. are all much within >> absolute max values, always, when MPU I/O pin is tristated, as well as when >> it is actively driven to 0 or 1. >> >> One difference with your design is that I don't use PWM, but I drive the >> NPN base directly via an algorithm (my MPU is doing much more than the >> buck part, it's a complex/articulated system), but it doesn't change the >> substance, as after reset you can enable the PWM module instead of bit >> banging the I/O pin like I do. >> >> >>> Thanks >> >> I'm really very glad if I had a chance to help you. >> >> Cheers, >> Mario >> >> >>> >>> Veronica >>> >>> >>> --