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'[PIC] PIC32 ipl7 not working correctly'
2012\02\02@134434 by Electron

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Hello,
on a(ny) PIC32 I can't get ipl7 interrupts working reliably, i.e. using the
register shadow set. Yes, I know there must be only one instance, and my level
7 interrupt is not re-entrant (as far as I know there can't even be level7 ints
called when one is already being served).

I'm not using and I don't want to use the standard library routines to manage
them, yet all the other <=6 levels work perfectly, just the 7 doesn't. Is there
anything special for level7 I'm missing, like a call to enable shadow set, etc..?

Interrupts get called but it looks like there's corruption going around. But,
as I said, only one interrupt is ipl7 and it certainly isn't reentrant.. so I
would expect it to work. :(

With kind regards,
Mario

2012\02\03@045042 by alan.b.pearce

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> I'm not using and I don't want to use the standard library routines to manage them,
> yet all the other <=6 levels work perfectly, just the 7 doesn't. Is there anything
> special for level7 I'm missing, like a call to enable shadow set, etc..?

I don't know about PIC32, but on PIC24 IIRC L7 interrupts are reserved for the error trap interrupts that the CPU itself generates. Are you sure you are allowed to have normal interrupt routines as L7 interrupts, as this would mean the trap routines cannot work.
-- Scanned by iCritical.

2012\02\03@121405 by William \Chops\ Westfield

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On Feb 2, 2012, at 10:44 AM, Electron wrote:

> I'm not using and I don't want to use the standard library routines to manage
> them, yet all the other <=6 levels work perfectly, just the 7 doesn't. Is there
> anything special for level7 I'm missing, like a call to enable shadow set, etc..?

So what are you using?  Don't you have to do something special to make sure that the alternate registers have a valid stack pointer (either having a separate stack, or updating the alternate SP from the main SP in the ISR)?

Does it work if you DO use the standard library routines?

When I was looking at it, I found the MIPS ISR preamble to be "weird." (Two "general purpose" registers reserved for the ISR to trash?  Really?)

BillW

2012\02\03@135338 by Electron

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At 10.50 2012.02.03, you wrote:
>
>> I'm not using and I don't want to use the standard library routines
>to manage them,
>> yet all the other <=6 levels work perfectly, just the 7 doesn't. Is
>there anything
>> special for level7 I'm missing, like a call to enable shadow set, etc..?
>
>I don't know about PIC32, but on PIC24 IIRC L7 interrupts are reserved
>for the error trap interrupts that the CPU itself generates. Are you
>sure you are allowed to have normal interrupt routines as L7
>interrupts, as this would mean the trap routines cannot work.

I couldn't find anywhere anything that suggested they cannot be used, I indeed
found references that they can, but they use the shadow register set.


At 18.13 2012.02.03, you wrote:
{Quote hidden}

I can't find enough documentation, and "Exploring the PIC32" doesn't help, either.

K0 and K1 registers are supposed to be used by the Kernel as temporary registers..
so it may be OK. I doubt that it is a compiler bug, as (probably) RTOS do use ipl7
CORE_TIMER as the base of their preemptive multitasking system.

But I just can't find in the docs anything that helps.

Yes I tried using standard libs, I tend to disassemble them and integrate the
juice into my own code, but in this case - to avoid risk of bugs - I called directly
INTEnableSystemMultiVectoredInt() and define the INT vectors appropriately... from
ipl1 to ipl6 all works wonders, ipl7 works too but then starts to misbehave..

Your idea that a second stack must be involved is very valid, but I just can't find
anything in the docs.

I hoped/hope some of You had already used ipl7 interrupts, met the problem and had
some light to share. I'd like to have one ipl7 INT, the CORE_TIMER actually, as in
this stage of my project it would really start to become useful to defer some jobs.

Cheers,
Mario


>BillW

2012\02\03@212043 by William \Chops\ Westfield

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On Feb 3, 2012, at 10:53 AM, Electron wrote:

>> When I was looking at it, I found the MIPS ISR preamble to be "weird."
>> (Two "general purpose" registers reserved for the ISR to trash?  Really?)
>
> I can't find enough documentation,

There is example code in the "interrupts" section of the pic32 manual.
See example 8.9 "Prologue With a Dedicated General Purpose Register Set in Assembly Code" in DS61108B, for example.

And there is the MIPS m4k documentation.

Also, MIPS seems to be a favorite architecture for college classes, and a google for "MIPS K0 K1" turns up pdfs, ppts, and quite a lot of info.  It seems to be a good/bad point for chips based on 3rd party cores.  On the good side there is all this extra documentation.  On the bad side, the actual chip vendor gets complacent about describing the details themselves in favor of "use the standard code."

I went searching when chipkit was having mysterious interrupt-related hangs..  Starting with the disassembled code: "It's not save K0 and K1!"  Search, search: "Oh, it just ... doesn't.  Wow."

It seems to me like it ought to be possible to write some really streamlined ISR code for MIPS.  Even without the extra register set, you've got two whole registers to play with; that ought to be enough to increment a systick timer...  But that doesn't seem to be what people do, and I don't see DISCUSSION.  Sigh.

BillW

2012\02\04@003506 by Mark Hanchey

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On 2/3/2012 9:19 PM, William "Chops" Westfield wrote:
> On Feb 3, 2012, at 10:53 AM, Electron wrote:
>
>>> When I was looking at it, I found the MIPS ISR preamble to be "weird."
>>> (Two "general purpose" registers reserved for the ISR to trash?  Really?)
>> I can't find enough documentation,
> There is example code in the "interrupts" section of the pic32 manual.
> See example 8.9 "Prologue With a Dedicated General Purpose Register Set in Assembly Code" in DS61108B, for example.
>
> And there is the MIPS m4k documentation.


Try to find a copy of the book, See Mips Run. It was invaluable to me when I was reverse engineering a mips powered bluray player.

Mark

2012\02\04@010016 by Mark Hanchey

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On 2/3/2012 1:53 PM, Electron wrote:
> I hoped/hope some of You had already used ipl7 interrupts, met the
> problem and had some light to share. I'd like to have one ipl7 INT,
> the CORE_TIMER actually, as in this stage of my project it would
> really start to become useful to defer some jobs. Cheers, Mario


Here is what my copy of 'see mips runs ' says about the interrupts on
mips and timer.
{Quote hidden}

Looks like it can be done but isn't recommended.
Mark

2012\02\04@021220 by William \Chops\ Westfield

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On Feb 3, 2012, at 9:59 PM, Mark Hanchey wrote:

>> it’s sometimes possible to share the counter/timer interrupt with an external device, but rarely a good idea to do so.

That description pre-dates the fancier vectored interrupt controller that is in the m4k cpu.  It looks like the IP vendors enhanced and included the interrupt controller (as part of the MIPS core, rather than a vendor-specific peripheral) as part of their attempts to court the embedded processor market (it's also one of the differences between ARM7 and CM3 cores...)

BillW

2012\02\04@181456 by Chris Roper

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You may find this page useful:

http://www.chipkit.org/wiki/index.php?title=Core_Function_Overview

It is related to how the ChipKit uses the Core Timer but has some
interesting comments about using it in general.

Cheers
Chris

On 3 February 2012 20:53, Electron <spam_OUTelectron2k4TakeThisOuTspaminfinito.it> wrote:

{Quote hidden}

>

2012\02\05@090347 by Electron

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Dear Chris,

At 00.14 2012.02.05, you wrote:
>You may find this page useful:
>
>http://www.chipkit.org/wiki/index.php?title=Core_Function_Overview
>
>It is related to how the ChipKit uses the Core Timer but has some
>interesting comments about using it in general.

Thanks, however I have the core timer working perfectly, the problem (not
just of the core timer, but of any interrupt) is if I go level 7.. all other
levels work great. It's clearly a shadow register set issue, maybe a bug of
this compiler version which just added support for the device (PIC32MX1XX)
I am using.

By the way, in the link You posted above, point 2 is wrong:

2.Do not do anything that could cause the CoreTimerHandler ISR to be called recursively. Primarily, this means do not enable interrupts as the core timer interrupt flag is still set and will immediately cause the system to call CoreTimerHandler ISR recursively.
This cannot happen, as if You enable (EI) interrupts, only interrupts of
higher priority than the one currently executing can interrupt the current
handler.

I don't know how to eMail the ChipKit developers, but to make them note this
would be good.

PS: I also have a PIC32MX3XX PIC, I will test the ipl7 vs <ipl7 issue there
as soon as I can write it up, and report.

With kind regards,
Mario

{Quote hidden}

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