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'[PIC] PIC ADC sampling, 2.2k impedance issue'
2006\06\23@225528 by Peter Todd

picon face
I built a quick circuit to take rough light level readings. It's a
18f458 PIC with a CdS photocell/1k resistor voltage divider connected to
AN0. The 1k resistor goes to 5v, the CdS phtocell to ground.

I noted the datasheet specifies that signal sources connected to the ADC
pins should have an impedance of less than 2.2k. My understanding is
that the voltage divider chain would not qualify for that in low light,
as the CdS photocell's max resistance in darkness is around 300k.

One thing I did do is connect an electrolite 100uF capacitor from ground
to AN0. My reasoning was that the capacitor could reduce the impedance
by providing a voltage source for the sampling period. Why the specific
one? Because there was one already sitting on the breadboard unused...

I'm taking 3.2uS samples about once a second, nothing hard by any means.
It all seems to work fine and the circuit smoothly goes from 1023 in
darkness to 53 with a really bright light hitting the CdS. Don't have
way for formally test it, but the application shouldn't really need it.

I'm just curious if my reasoning was correct. What do you guys think?

--
spam_OUTpeteTakeThisOuTspampetertodd.ca http://www.petertodd.ca

2006\06\23@232132 by Spehro Pefhany

picon face
At 11:15 PM 6/23/2006 -0400, you wrote:
>I built a quick circuit to take rough light level readings. It's a
>18f458 PIC with a CdS photocell/1k resistor voltage divider connected to
>AN0. The 1k resistor goes to 5v, the CdS phtocell to ground.
>
>I noted the datasheet specifies that signal sources connected to the ADC
>pins should have an impedance of less than 2.2k. My understanding is
>that the voltage divider chain would not qualify for that in low light,
>as the CdS photocell's max resistance in darkness is around 300k.

The Thevenin equivalent source resistance (assuming a regulated Vdd line)
is the LDR in  parallel with 1K , so it will always be less than 1K.

Rs = Rx || 1K = (Rx * 1K)/(Rx + 1K)

>Best regards,

Spehro Pefhany --"it's the network..."            "The Journey is the reward"
.....speffKILLspamspam@spam@interlog.com             Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog  Info for designers:  http://www.speff.com
->>Test equipment, parts OLED displys http://search.ebay.com/_W0QQsassZspeff


2006\06\24@020440 by Peter Todd

picon face
On Fri, Jun 23, 2006 at 11:33:41PM -0400, Spehro Pefhany wrote:
> At 11:15 PM 6/23/2006 -0400, you wrote:
> >I built a quick circuit to take rough light level readings. It's a
> >18f458 PIC with a CdS photocell/1k resistor voltage divider connected to
> >AN0. The 1k resistor goes to 5v, the CdS phtocell to ground.
> >
> >I noted the datasheet specifies that signal sources connected to the ADC
> >pins should have an impedance of less than 2.2k. My understanding is
> >that the voltage divider chain would not qualify for that in low light,
> >as the CdS photocell's max resistance in darkness is around 300k.
>
> The Thevenin equivalent source resistance (assuming a regulated Vdd line)
> is the LDR in  parallel with 1K , so it will always be less than 1K.
>
> Rs = Rx || 1K = (Rx * 1K)/(Rx + 1K)

Thanks, I think I understand it a lot better now.


With a fair bit of work I was able to kludge together an equation that I
think describes the final voltage vs. lux graph accurately with gnuplot.
Not exactly the most linear of things, but at least I can see that my
intuitive choice of 1k isn't that great a pick... If I got everything
right, something more like 220ohms would still give me sensitivity at
both ends, 1k ends up at a zero slope long before the CdS saturates.

--
petespamKILLspampetertodd.ca http://www.petertodd.ca

2006\06\24@023550 by PicDude

flavicon
face
Firstly, I use 16F PICs which specify min impedance of 10k, so was not aware
of this change.  I just checked the datasheet for a 18F452 and it says 2.5K,
but you can go to 10k with higher acquisition times.  Just an FYI.

I would think that the capacitor would introduce errors, but not sure if that
matters to your app.

However in your app, with an ideal voltage source having 0 ohms resistance,
for the purposes of the A/D converter, it should A/D should see an impedance
of 1K in parallel with the CdS's resistance, making the capacitor
unnecessary.

Cheers,
-Neil.



On Friday 23 June 2006 22:15, Peter Todd wrote:
{Quote hidden}

2006\06\24@081743 by olin piclist

face picon face
Peter Todd wrote:
> The 1k resistor goes to 5v, the CdS phtocell to ground.
> I noted the datasheet specifies that signal sources connected to the
> ADC pins should have an impedance of less than 2.2k. My understanding
> is that the voltage divider chain would not qualify for that in low
> light, as the CdS photocell's max resistance in darkness is around
> 300k.

The total impedence into the A/D pin can not exceed the 1Kohm pullup
resistor.  Think about it.  If the photoresistor (it is NOT a photocell)
were completely removed (infinite impedence), you'd still have a source
impedence of 1Kohms into the A/D input.

> One thing I did do is connect an electrolite 100uF capacitor from
> ground to AN0. My reasoning was that the capacitor could reduce the
> impedance by providing a voltage source for the sampling period.

Some capacitance to ground is good to reduce random noise.  However it does
nothing to compensate for low source impedence.  The overall leakage plus
charge current into the A/D pin is still the same.  The capacitor will
merely average out the resulting voltage drop due to the source impedence.


******************************************************************
Embed Inc, Littleton Massachusetts, (978) 742-9014.  #1 PIC
consultant in 2004 program year.  http://www.embedinc.com/products

2006\06\24@082742 by olin piclist

face picon face
Peter Todd wrote:
> I got everything right, something more like 220ohms would still give
> me sensitivity at both ends,

Just keep in mind that this will draw up to 23mA in very bright light.

> 1k ends up at a zero slope long
> before the CdS saturates.

Your circuit will be most sensitive to variations in the cell resistance at
mid range.  In other words, when the cell resistance equals the pullup
resistance.  The important question is what range of light you care about.
Measure the cell resistance at the two extremes, then design your circuit to
resolve that range at the required accuracy.


******************************************************************
Embed Inc, Littleton Massachusetts, (978) 742-9014.  #1 PIC
consultant in 2004 program year.  http://www.embedinc.com/products

2006\06\24@085204 by Spehro Pefhany

picon face
At 02:24 AM 6/24/2006 -0400, you wrote:


>With a fair bit of work I was able to kludge together an equation that I
>think describes the final voltage vs. lux graph accurately with gnuplot.
>Not exactly the most linear of things, but at least I can see that my
>intuitive choice of 1k isn't that great a pick... If I got everything
>right, something more like 220ohms would still give me sensitivity at
>both ends, 1k ends up at a zero slope long before the CdS saturates.

Your worst case power dissipation in the LDR would be around 30mW, which
might be enough to adversely affect a small photocell*.

* yes

>Best regards,

Spehro Pefhany --"it's the network..."            "The Journey is the reward"
EraseMEspeffspam_OUTspamTakeThisOuTinterlog.com             Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog  Info for designers:  http://www.speff.com
->>Test equipment, parts OLED displys http://search.ebay.com/_W0QQsassZspeff


2006\06\26@004157 by Peter Todd

picon face
part 1 2304 bytes content-type:text/plain; charset=us-asciiOn Sat, Jun 24, 2006 at 08:27:44AM -0400, Olin Lathrop wrote:
> Peter Todd wrote:
> > I got everything right, something more like 220ohms would still give
> > me sensitivity at both ends,
>
> Just keep in mind that this will draw up to 23mA in very bright light.

Heck, looks like I was wrong, I don't need more sensitivity at all.
Given that the final application is intended for light levels up to a
office well light though a window, the direct sunlight that a resistor
value of 220 ohms would capture is *far* brighter than what I need. I
ended up using a resistor of 4.7k, which seems to work and makes nice
graphs.

> > 1k ends up at a zero slope long
> > before the CdS saturates.
>
> Your circuit will be most sensitive to variations in the cell resistance at
> mid range.  In other words, when the cell resistance equals the pullup
> resistance.  The important question is what range of light you care about.
> Measure the cell resistance at the two extremes, then design your circuit to
> resolve that range at the required accuracy.

Makes sense, the slope of the graph I generated was pretty much linear
in the midrange, not at all at the extremes.


If anyone is interested I attached a screenshot of the light levels
graph I made today. The logging system is pretty brute force, the PIC
outputs an ASCII stream of abc 123 def at 2400 baud. A cron-job on a
spare Linux box picks out one entry per minute and records it to a log
file, timestamped with a seconds from 1970 UNIX time. The graph is
simply that file piped to xgraph, that's why the xaxis looks so odd.
Works though.

It's all sitting next to a west facing window on the third floor of a
house. Looks like light levels get highest later in the day as the sun
is in almost direct view. (the sensor itself is horizontal, and recieves
it's light from bouncing off the white walls around it) The floor is
unused so all variations, like the jagged sections, must be either the
circuit, or the light outside. Tree brances maybe? Not really sure, the
graph is fairly smooth when you zoom in.

Gonna leave all this running for awhile to get data before I build my
sealed light meter things that I mentioned to you guys a few months ago.

--
petespamspam_OUTpetertodd.ca http://www.petertodd.ca


part 2 20176 bytes content-type:image/png (decode)


part 3 35 bytes content-type:text/plain; charset="us-ascii"
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