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'[PIC] Overloading interrupts...'
2009\03\31@155552 by solarwind

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What happens when interrupts are received faster than the time
required for the ISR to complete?

For example, let's say I'm interrupting on UART receive, every time I
receive a byte, so I can process it. However, the ISR may take a
considerable amount of time to complete (hypothetical situation).
Since there may be a possibility of receiving data really fast, the
interrupt will be "hit" multiple times before the ISR has time to
complete. What happens in this case? Does the ISR reset and go back to
the beginning? Or does nothing happen until the ISR has completed?

--
solarwind

2009\03\31@161135 by Bob Blick

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On Tue, 31 Mar 2009 14:55:51 -0500, "solarwind"
<spam_OUTx.solarwind.xTakeThisOuTspamgmail.com> said:
> What happens when interrupts are received faster than the time
> required for the ISR to complete?
>
> For example, let's say I'm interrupting on UART receive, every time I
> receive a byte, so I can process it. However, the ISR may take a
> considerable amount of time to complete (hypothetical situation).
> Since there may be a possibility of receiving data really fast, the
> interrupt will be "hit" multiple times before the ISR has time to
> complete. What happens in this case? Does the ISR reset and go back to
> the beginning? Or does nothing happen until the ISR has completed?

On the single-vector chips, when an interrupt happens global interrupt
enable is disabled, so your interrupt just completes as it normally
would. If you then RETFIE, if any interrupt flags are lit, boom, you get
another interrupt generated and back in you go.

In your interrupt routine, you check the flag for each enabled interrupt
source in turn, and when you find one, clear it immediately and service
it.

Cheerful regards,

Bob

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2009\03\31@161737 by Jan-Erik Soderholm

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solarwind wrote:
> What happens when interrupts are received faster than the time
> required for the ISR to complete?
>
> For example, let's say I'm interrupting on UART receive, every time I
> receive a byte, so I can process it. However, the ISR may take a
> considerable amount of time to complete (hypothetical situation).
> Since there may be a possibility of receiving data really fast, the
> interrupt will be "hit" multiple times before the ISR has time to
> complete. What happens in this case? Does the ISR reset and go back to
> the beginning?

No nothing happens until the RETFIE instruction executes.
Then it re-triggers the ISR at once if there happens to
be some xxxF flag set at the time the RETFIE executes.

> Or does nothing happen until the ISR has completed?

Correct.

(Check the PIC18 series for slight variations to this, but
not realy rellevant as long as we are talkning about the
same interrupt source.

So in your case with the USART, a burst of *2* could easily
be handled with the second waiting in the USART buffer util
the first interrupt has executed.

It's nothing but rather simple timing calculations realy...

The simple solution is of course to make sure that the worst-
case run-time of the ISR is less then the time between two
carachters through the USART.

Jan-Erik.

2009\03\31@173801 by olin piclist

face picon face
solarwind wrote:
> What happens when interrupts are received faster than the time
> required for the ISR to complete?

The interrupt routine is re-entered as soon as interrupts are turned back on
by the RETFIE instruction.  This is because another interrupt condition is
pending and it causes a interrupt as soon as interrupts are globally
enabled.


********************************************************************
Embed Inc, Littleton Massachusetts, http://www.embedinc.com/products
(978) 742-9014.  Gold level PIC consultants since 2000.


'[PIC] Overloading interrupts...'
2009\04\01@063911 by Michael Rigby-Jones
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> -----Original Message-----
> From: .....piclist-bouncesKILLspamspam@spam@mit.edu [piclist-bouncesspamKILLspammit.edu] On
Behalf
> Of solarwind
> Sent: 31 March 2009 20:56
> To: Microcontroller discussion list - Public.
> Subject: [PIC] Overloading interrupts...
>
> What happens when interrupts are received faster than the time
> required for the ISR to complete?
>
> For example, let's say I'm interrupting on UART receive, every time I
> receive a byte, so I can process it. However, the ISR may take a
> considerable amount of time to complete (hypothetical situation).
> Since there may be a possibility of receiving data really fast, the
> interrupt will be "hit" multiple times before the ISR has time to
> complete. What happens in this case? Does the ISR reset and go back to
> the beginning? Or does nothing happen until the ISR has completed?

Other have explained what would happen, but something to be aware of in
the case of the UART is that you will start losing data once the
hardware FIFO buffer is full.

The bottom line is that ISR's should in most cases be designed to run as
quickly as possible. In the case of a comms interrupt you would normally
just take the data out of the UART register and add it to a circular
buffer.  Your main program loop can than take data out of the buffer
when it needs to.

Regards

Mike

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2009\04\01@074256 by olin piclist

face picon face
Michael Rigby-Jones wrote:
> The bottom line is that ISR's should in most cases be designed to run
> as quickly as possible. In the case of a comms interrupt you would
> normally just take the data out of the UART register and add it to a
> circular buffer.  Your main program loop can than take data out of
> the buffer when it needs to.

Yes, and note how long you have to service the UART.  At 115.2Kbaud there
can be a character every 86.8uS, which is 434 instructions on a 20MHz PIC.
The interrupt routine to grab a byte from the UART and stuff it into a FIFO
should be only a small fraction of that.


********************************************************************
Embed Inc, Littleton Massachusetts, http://www.embedinc.com/products
(978) 742-9014.  Gold level PIC consultants since 2000.

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