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'[PIC] More MSSP Questions...'
2006\03\20@231531 by Josh Koffman

face picon face
Alright, I've been reading the datasheet and now I have more questions
(go figure)!

I've been looking at DS39631A - the PIC18F2520 datasheet.

On page 166 (section 17.3.5 Master Mode) it's talking about the SPI
clock rate and how we can select it. The following options are given:

Fosc/4 (or Tcy)
Fosc/16 (or 4 . Tcy)
Fosc/64 (or 16 . Tcy)
Timer2 Output/2

So my question is...should the dot that preceeds the Tcy be something
else? If it really does mean multiplied by, I just don't understand
it...Fosc/16 should be 1/4 the instruction speed correct?

Second, am I correct in determining that if I want to clock data out
of my wireless module, I should keep my PIC in master mode so that it
generates the clock signal? If so, from my understanding I need to
write a byte to the SSPBUF register. At that point my data will be
clocked out as the incominging data is clocked back into SSPBUF.

This poses a problem that I mentioned in my other email. Since I need
to connect SDI and SDO of the PIC together somehow as my wireless
module only has one data connection, I have an issue in receive mode.
When I'm transmitting to the module, I'm ok as I can just ignore
whatever is clocked back into SSPBUF as I send my byte. That won't
work when I want to receive though...I have to load SSPBUF with
something to trigger it to receive and since the pins are connected
together I'll just end up reading back in what I'm sending. Or even
worse, I'll  create a bus contention and damage my module or PIC pins.
What do I do?

Thanks!

Josh
--
A common mistake that people make when trying to design something
completely foolproof is to underestimate the ingenuity of complete
fools.
       -Douglas Adams

2006\03\21@002710 by Sergey Dryga

face picon face
Josh Koffman <joshybear <at> gmail.com> writes:

Hello Josh,
>
> Alright, I've been reading the datasheet and now I have more questions
> (go figure)!
>
> I've been looking at DS39631A - the PIC18F2520 datasheet.
>
> On page 166 (section 17.3.5 Master Mode) it's talking about the SPI
> clock rate and how we can select it. The following options are given:
>
> Fosc/4 (or Tcy)
> Fosc/16 (or 4 . Tcy)
> Fosc/64 (or 16 . Tcy)
> Timer2 Output/2
>
> So my question is...should the dot that preceeds the Tcy be something
> else? If it really does mean multiplied by, I just don't understand
> it...Fosc/16 should be 1/4 the instruction speed correct?

It takes 4 clock cycles for one instruction, therefore Tcy = 1/(Fosc/4).
One way to think about it is that "frequency" of instructions is Fosc/4.  
For MSSP clock speed Fosc/16 you will have Fmssp = Fosc/16, while period of the
clock Tmssp = 4*Tcy.  


>
> Second, am I correct in determining that if I want to clock data out
> of my wireless module, I should keep my PIC in master mode so that it
> generates the clock signal? If so, from my understanding I need to
> write a byte to the SSPBUF register. At that point my data will be
> clocked out as the incominging data is clocked back into SSPBUF.
>

I did not use MSSP in SPI mode, but in I2C the module will first clock out
address and indicate read/write mode (last bit of the address).  Slave will
provide data if master requests a read.  The master provides the clock.

<SNIP>

Sergey Dryga
Beaglerobotics.com

2006\03\21@041036 by Alan B. Pearce

face picon face
>Second, am I correct in determining that if I want to
>clock data out of my wireless module, I should keep my
>PIC in master mode so that it generates the clock signal?
>If so, from my understanding I need to write a byte to
>the SSPBUF register. At that point my data will be
>clocked out as the incominging data is clocked back
>into SSPBUF.

I do not know the wireless modules you are using, but does the receive end
expect the micro to be operating in master or slave mode? If master mode
then presumably it has a dual port ram or FIFO that it can load, and the
micro then empties. If slave mode, then you will need to switch the MSSP
between modes as you move from transmit to receive.


>This poses a problem that I mentioned in my other email.
>Since I need to connect SDI and SDO of the PIC together
>somehow as my wireless module only has one data connection,

You put a resistor between SDI and SDO. Have a look at the FTDI232B
datasheet (not the R version) for how they attach an EEPROM for
configuration data, as they have the same problem.

2006\03\21@065800 by Jan-Erik Soderholm

face picon face
Josh Koffman wrote :

> On page 166 (section 17.3.5 Master Mode) it's talking about the SPI
> clock rate and how we can select it. The following options are
given:
>
> Fosc/4 (or Tcy)
> Fosc/16 (or 4 . Tcy)
> Fosc/64 (or 16 . Tcy)
> Timer2 Output/2
>
> So my question is...should the dot that preceeds the Tcy
> be something else?

Yes, an multiplication sign.

> If it really does mean multiplied by, I just don't understand
> it...Fosc/16 should be 1/4 the instruction speed correct?

Fosc is a *frequency*.
Tcy is a *time*.

Lower Fosc ==> higher Tcy.

I think you've mixed that up...

Jan-Erik.



2006\03\21@120129 by Josh Koffman

face picon face
On 3/21/06, Alan B. Pearce <spam_OUTA.B.PearceTakeThisOuTspamrl.ac.uk> wrote:
> >Second, am I correct in determining that if I want to
> >clock data out of my wireless module, I should keep my
> >PIC in master mode so that it generates the clock signal?
> >If so, from my understanding I need to write a byte to
> >the SSPBUF register. At that point my data will be
> >clocked out as the incominging data is clocked back
> >into SSPBUF.
>
> I do not know the wireless modules you are using, but does the receive end
> expect the micro to be operating in master or slave mode? If master mode
> then presumably it has a dual port ram or FIFO that it can load, and the
> micro then empties. If slave mode, then you will need to switch the MSSP
> between modes as you move from transmit to receive.

I believe the PIC should be in master mode as it needs to supply the
clock signal. The wireless module does have a FIFO as far as I
understand.

> >This poses a problem that I mentioned in my other email.
> >Since I need to connect SDI and SDO of the PIC together
> >somehow as my wireless module only has one data connection,
>
> You put a resistor between SDI and SDO. Have a look at the FTDI232B
> datasheet (not the R version) for how they attach an EEPROM for
> configuration data, as they have the same problem.

Interesting...I checked this out. The datasheet I looked at is located
at http://www.ftdichip.com/Documents/DataSheets/ds232b18.pdf and the
interesting page is 14. Just so I'm clear...this works because the
resistor os on the SDO line of the PIC. When the PIC is sending data,
it drives through the resistor and all is fine. There is no data
coming out of the wireless module, and the SDI pin basically clocks in
whatever the SDO pin clocks out. When the PIC is receiving data, I
write a dummy byte to SSPBUF and the PIC starts clocking it out while
clocking in whatever is on SDI. If SDO and SDI are in contention (for
instance if the PIC outputs a 0 bit but the wireless module outputs a
1 bit), due to the resistor, the wireless module wins, and all is
happy.

So if my understanding is correct, is a 2.2K resistor a reasonable
value for this?

Thanks!

Josh
--
A common mistake that people make when trying to design something
completely foolproof is to underestimate the ingenuity of complete
fools.
       -Douglas Adams

2006\03\22@035052 by Alan B. Pearce

face picon face
>Interesting...I checked this out. The datasheet I
>looked at is located at
www.ftdichip.com/Documents/DataSheets/ds232b18.pdf
>and the interesting page is 14. Just so I'm clear...
>this works because the resistor os on the SDO line
>of the PIC. When the PIC is sending data, it drives
>through the resistor and all is fine. ...

> If SDO and SDI are in contention (for instance
>if the PIC outputs a 0 bit but the wireless module
>outputs a 1 bit), due to the resistor, the wireless
>module wins, and all is happy.

Essentially yes. Remember the output of the wireless module is tristate, so
it is a high impedance when receiving data from the micro, and pulls high
and low when transmitting data to the micro.

>So if my understanding is correct, is a 2.2K
>resistor a reasonable value for this?

It would seem reasonable. The limitation for low value is the output current
of the wireless module when pulling in the opposite direction to the SDO
output, while still maintaining a suitable logic level. You could possibly
go a bit higher, say 4k7 to 10k, depending on the combined input capacitance
of the SDI and wireless module inputs and the clock speed you wish to use.
But 2k2 looks to be a pretty reasonable starting value, without looking up
any figures in datasheets.

2006\03\22@094255 by Josh Koffman

face picon face
On 3/22/06, Alan B. Pearce <.....A.B.PearceKILLspamspam@spam@rl.ac.uk> wrote:
> >So if my understanding is correct, is a 2.2K
> >resistor a reasonable value for this?
>
> It would seem reasonable. The limitation for low value is the output current
> of the wireless module when pulling in the opposite direction to the SDO
> output, while still maintaining a suitable logic level. You could possibly
> go a bit higher, say 4k7 to 10k, depending on the combined input capacitance
> of the SDI and wireless module inputs and the clock speed you wish to use.
> But 2k2 looks to be a pretty reasonable starting value, without looking up
> any figures in datasheets.

Thanks Alan! That's just what I needed to hear.

Josh
--
A common mistake that people make when trying to design something
completely foolproof is to underestimate the ingenuity of complete
fools.
       -Douglas Adams

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