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'[PIC] Hardware DO instruction on ds30F'
2005\08\18@141008 by John Nall

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The hardware DO loop instruction on the ds30F architecture (along with
the hardware to support the instruction) is interesting.  First time
I've ever encountered it.  Is that on any of the other PIC chips?  Or is
confined to the ds30F  family?

John

2005\08\18@143535 by olin piclist

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John Nall wrote:
> The hardware DO loop instruction on the ds30F architecture (along with
> the hardware to support the instruction) is interesting.  First time
> I've ever encountered it.  Is that on any of the other PIC chips?  Or is
> confined to the ds30F  family?

It's only on the dsPIC so far.

Keep in mind that there are only two DO loop nesting levels in the hardware.
Unless you want to swap the hardware state in software (which gets messy),
you have to think about allocating the levels.  In practise this isn't much
of an issue, but you do have to think about it.

For example, on a current 30F4012 project I'm using one DO level in the
highest priority interrupt routine and leaving the remaining level for other
code.  That means that none of the other interrupt routines are allowed to
use DO at all, since that could result in 3 levels if the foreground code
uses DO, a low priority interrupt, and the high priority interrupt.


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2005\08\18@150408 by John Nall

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Olin Lathrop wrote:

> > Keep in mind that there are only two DO loop nesting levels in the
> hardware.
> Unless you want to swap the hardware state in software (which gets
> messy),
> you have to think about allocating the levels.  In practise this isn't
> much
> of an issue, but you do have to think about it.

Yes, I can see where it could be a problem.  Certainly in theory, if not
in practice.  Thanks for the heads up.  I'll make notes on such things
as I go along.  Might be enough "gotcha's" there to justify a revised
version of LINT.  :-)

John

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