Post by thread:[PIC] ECCP/CCP with an 18F4550

> Slightly confused; I need to drive a transformer in a push pull mode with > 2 FET's from the PIC. I wonder whether the ECCP mode is much suitable to do that > (since I will get CCP2 free in this case), or whether it is better to use > CCP1 and CCP2 to drive the FET's. I think you may find this is one of the reasons why they introduced the ECCP module. I think you will find it has methods for setting dead time and other such requirements. I haven't used the ECCP module in this way, so am not qualified to talk 'with knowledge' but seem to remember these were areas it improved over the CCP. -- Scanned by iCritical.

On Thu, May 31, 2012 at 8:51 PM, <spam_OUTalan.b.pearceTakeThisOuTstfc.ac.uk> wrote: >> Slightly confused; I need to drive a transformer in a push pull mode with >> 2 FET's from the PIC. I wonder whether the ECCP mode is much suitable to do that >> (since I will get CCP2 free in this case), or whether it is better to use >> CCP1 and CCP2 to drive the FET's. > > I think you may find this is one of the reasons why they introduced the ECCP module. I think you will find it has methods for setting dead time and other such requirements. I haven't used the ECCP module in this way, so am not qualified to talk 'with knowledge' but seem to remember these were areas it improved over the CCP. I found the dead time a good feature, so I decided to give it a try. I did some quick testing with a sine table taken from Roman Black's 1kHz sinewave generator http://www.romanblack.com/onesec/Sine1kHz.htm using the following code. #include <p18f4550.h> #include <delays.h> #include <timers.h> #include <pwm.h> #include "stdint.h" #pragma config WDT = OFF #pragma config PLLDIV = 5 /* 20MHz / 5 = 4 MHz, 96MHz PLL i/p */ #pragma config CPUDIV = OSC1_PLL2 /* CPU CLK = 96 MHz/2 = 48MHz */ #pragma config USBDIV = 2 /* 96MHz PLL/2 = 48MHz USB clock */ #pragma config FOSC = HSPLL_HS /* Osc type: HS Crystal, PLL enabled */ #pragma config VREGEN = ON /* USB Internal Voltage Regulator enabled */ #pragma config PWRT = ON #pragma config MCLRE = OFF #pragma config LVP = OFF #pragma config BOR = OFF /* * this is the 50 entry "harmonic compensated" * sine table (updated 20th Jun 2011) */ const rom char sine[50] = { 52, 57, 62, 66, 70, 74, 77, 80, 82, 84, 85, 86, 86, 86, 85, 83, 81, 78, 75, 72, 69, 65, 61, 56, 52, 48, 44, 39, 35, 31, 28, 25, 22, 19, 17, 15, 14, 14, 14, 15, 16, 18, 20, 23, 26, 30, 34, 38, 43, 48 }; void main (void) { char dc = 0; char step = 0; TRISCbits.TRISC2 = 0; /* P1A output */ TRISDbits.TRISD5 = 0; /* P1B output */ /* * Half bridge mode * P1A & P1B used, Active HIGH */ SetOutputPWM1(HALF_OUT, PWM_MODE_1); /* * start PWM * 1PWM cycle/period = 100ticks */ OpenPWM1(100 - 1); /* * CPU CLK = 48MHz * Tcy = 4/48MHz = 1/12uS = 83.3nS * ie, Nop() = 84nS * 1tick = 16*84nS = 1344nS = 1.344uS; * 100ticks = 134.4uS * PWM freq = 1/134.4uS = 7.4404kHz * * PWM freq = 50Hz */ T2CON = 0b00000100; /* TMR2 ON, 1:1 post, 1:16 pre */ while (1) { while (!PIR1bits.TMR2IF); dc = sine[step]; SetDCPWM1(dc); /* setup new duty cycle */ PIR1bits.TMR2IF = 0; step++; if (step >= 50) step = 0; } } However the output waveform doesn't seem to be as expected ? I find that the P1B is high most of the time, while P1A low. At least the duty cycle should vary a bit more consistently ? Feeling even more confused by now, whether it is the implementation what I did, or is it due to the ECCP, or in fact whether this what's to be expected... P1B http://www.flickr.com/photos/79743192@N07/7308947670/in/photostream P1A http://www.flickr.com/photos/79743192@N07/7308947960/in/photostream Any ideas ? Best Regards, Manu