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'[PIC] Converting 16F84 DCC decoder to 16F628 (or 1'
2007\04\02@053652 by Jan van Dijk

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Hello all,

I'm currently in the process of constructing a dcc decoder for controlling a
LGB train. I've found the scheme for a dcc decoder at
http://technology.niagarac.on.ca/staff/mcsele/dcc.htm It's based upon a
16F84 and the assembly code is also available:
technology.niagarac.on.ca/staff/mcsele/decoder.asm
Since the 16F84 is 'obsolete' I was planning on using an 16F628 for the
decoder... Would it work if I just re-compiled the given assembly source to
the 16F628 chip? Any special things I should look in to when converting the
program?

Also, the original scheme is based on a 8MHz crystal. I'm planning on using
a 20 MHz one... if I changed the rtcc divider from 32 to 80, would that do
the trick?

Of course, the best way to find out, it to actually build / programm the
chip, but I don't have all the parts yet, and thought I would inquire so I
might save me some troubles :)

Best regards and thanks in advance,

Jan

2007\04\02@060519 by Pic

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Hi Jan,

Have a look at http://www.merg.info/kits.htm . They have more uptodate
information on building your own DCC decoder. Even kits are available and
ASM files as well using the 16F628.

Regards

Harry (MERG member)

{Quote hidden}

> -

2007\04\02@063224 by Jan van Dijk

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Hello Harry,

Thanks for your fast reply. A lot of DCC decoders are available at the web,
and I choose the one I mentioned because of the simplicity of the design.
If the current design doesn't work out, I might check out that merg club...
although I generally prefer free available schemes above restricted
schemes...

Best regards,

Jan


2007/4/2, .....picKILLspamspam.....harry-arends.nl <EraseMEpicspam_OUTspamTakeThisOuTharry-arends.nl>:
{Quote hidden}

2007\04\02@095942 by Pic

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Then look at
http://www.merg.info/resources/dcc.htm#Filesfordownloading

{Quote hidden}

>

2007\04\02@103438 by Jan van Dijk

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Thanks for the info, but I'd rather get the originally posted scheme to
work, so the questions still remain :)

Best regards,

Jan


2007/4/2, RemoveMEpicspam_OUTspamKILLspamharry-arends.nl <RemoveMEpicTakeThisOuTspamspamharry-arends.nl>:
{Quote hidden}

> >

2007\04\02@161226 by Steve Smith

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Well if you replace all the labels 'config' with con_fig it compiles for a
628 in mp lab but I haven't looked at the functional differences between the
parts shouldn't be too bad

Steve

{Original Message removed}

2007\04\02@163820 by Herbert Graf

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On Mon, 2007-04-02 at 21:11 +0100, Steve Smith wrote:
> Well if you replace all the labels 'config' with con_fig it compiles for a
> 628 in mp lab but I haven't looked at the functional differences between the
> parts shouldn't be too bad

Hello Steve,

There are a few issues you must look in to.

First off, yes, you have to "translate" the config settings to the 628.
Generally the 628 has "more" stuff in the config section, so you must
turn off the things that the 16F84 doesn't have that may interfere with
operation.

Second, the analog comparators in the 628 have to be turned off, by
default they are on.

Third, and this is the one that either is zero work or TONS of work: you
have to look at how the assembly is written. If the writers used the
MChip include files, and did proper work with the bank settings (i.e.
using BANKSEL) you should be OK. However, if they defined their own
symbols for FSRs, or, even worse, used the numeric values you have ALOT
of work ahead of you.

Same with general RAM, if they did things proper you should be fine, if
they used "defines" with absolute numbers then you may have alot of work
ahead of you.

Good luck!

TTYL

2007\04\05@061302 by Jan van Dijk

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Hello,

Thanks for the given input! I made a MPLAB project and added the assembler
file to it. The code compiles when renaming the config to con_fig, but no
include files are used...

The control registers are defined in the program start:

*;Variable definition - PIC16C84 control registers.*

*f0      equ     00
rtcc    equ     01
pc      equ     02
status  equ     03
carry   equ    0
zbit    equ    2
rp0     equ    5
rp1     equ    6
fsr     equ     04
porta   equ     05
portb   equ     06
eedata  equ     08
eeadr   equ     09
eecon1  equ     08
rd      equ    0
wr      equ    1
wren    equ    2
eecon2  equ     09
pclath  equ     0A
intcon  equ     0B
f       equ    1
w       equ*    0

And they are used in the program... also some 'magical' numbers are used
within the code to set the registers:

*;Init sets porta as all outputs, pin b0 as input and the rest of portb as
;outputs and sets the rtcc counter to divide by 32 (16us at 8MHz clock).
;FSR is set to 88h for indirect access to INTCON register from page 00.*

*Init    movlw   b'00000001'     ;RA0=input, RA1,2=outputs
       tris    porta
       clrf    porta
       movlw   0x00            ;All of PortB = outputs
       tris    portb
       clrf    portb
       clrf    intcon
       movlw   0x84
       option
       movlw   0x88
       movwf   fsr*

Luckily the code is well documented... but I might have to do some puzzling
then :)

Best regards,

Jan



2007/4/2, Herbert Graf <spamBeGonemailinglist3spamKILLspamfarcite.net>:
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> -

2007\04\05@093557 by Jan van Dijk

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Okay, I'm altering the original file so it will work again with the 16C84,
but with using the microchip include file...

I found a rather strange thing, all registers maps to the register which are
defined in the P16C84.INC, only 2 do not:

assembly file DECODER.ASM:
eecon1  equ     08
rd      equ    0
wr      equ    1
wren    equ    2
eecon2  equ     09

include file P16C84:
EECON1                       EQU     H'0088'
EECON2                       EQU     H'0089'

These addresses are actually used, which rather surpises me, since they
don't match with the include file:

;Generic EE write subroutine that writes eedata into eeadr. If the processor
;is busy with a previous write operation, the subroutine returns without
;writing. Inputs are eeadr and eeread.

EEwrite movlw   0x55
       movwf   eecon2
       movlw   0xAA
       movwf   eecon2
       bsf     eecon1,wr
eewrcon btfsc   eecon1,wr
       goto    eewrcon
       bcf     eecon1,wren
       bcf     status,rp0
       return

Is there anyone who might have a clue what's going on?

Best regards,

Jan


2007/4/5, Jan van Dijk <.....iwritecodespam_OUTspamgmail.com>:
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2007\04\05@114338 by Maarten Hofman

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Redwood Shores,  5 april 2007.

The creator of the definitions wanted to avoid the irritating warning
regarding the register not being in page 0, and therefore left out the 0x80,
which would make it part of page 1. As you have to set the bank bit
correctly anyway, the behaviour is unchanged. When coding absolute code, the
same thing is often acomplished by adding ^ 0x80 to a register. Of course,
just disabling the errorlevel once you set the page bits, and resetting it
once you reset them can be better... Or disable the warning alltogether, as
it is a bit silly (especially if you're not coding in absolute mode).

Greetings,
Maarten Hofman.

2007\04\05@124148 by alan smith

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was it the 'F84 that had its reset vector at the bottom....or was that C54?  I recall....one of them did, and you had to watch that when going back and forth.

---------------------------------
Don't pick lemons.
See all the new 2007 cars at Yahoo! Autos.

2007\04\05@154715 by Steve Smith

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That was the C54,56 ect the C84 was 0

Steve

-----Original Message-----
From: TakeThisOuTpiclist-bouncesKILLspamspamspammit.edu [.....piclist-bouncesspamRemoveMEmit.edu] On Behalf Of
alan smith
Sent: 05 April 2007 17:42
To: Microcontroller discussion list - Public.
Subject: RE: [PIC] Converting 16F84 DCC decoder to 16F628 (or 16F648)

was it the 'F84 that had its reset vector at the bottom....or was that C54?
I recall....one of them did, and you had to watch that when going back and
forth.

---------------------------------
Don't pick lemons.
See all the new 2007 cars at Yahoo! Autos.

2007\04\05@161120 by Steve Smith

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You will need a pair of lines in the startup

Movlw                07h                ; Val for all digital
Movwf                CMCON                ; for the CMCON reg

Rgds Steve

{Original Message removed}

2007\04\05@222857 by michael brown

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Steve Smith wrote:
> You will need a pair of lines in the startup
>
> Movlw 07h ; Val for all digital
> Movwf CMCON ; for the CMCON reg

That is correct, and he will also need to move all the variables
currently attempting to occupy RAM locations 0x0C thru 0x1F.  On the
16F628, free RAM starts at 0x20.  Outside of that, I can't think of
anything else he needs to do different.

2007\04\06@013039 by Jan van Dijk

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Great! :-)

Thanks for all the replies guys! This should get me in the right
direction... I'll post an update when I'm done (or encounter other
problems!)

Happy Easter,

Jan


2007/4/6, michael brown <RemoveMEn5qmgspamspamBeGoneearthlink.net>:
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> -

2007\04\06@090231 by Jan van Dijk

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The EEDATA & EEADR moved from bank 0 to bank 1, so a lot more bank switching
code has to be added... apart from that... all seems to be going well...

2007/4/6, Jan van Dijk <spamBeGoneiwritecode@spam@spamspam_OUTgmail.com>:
{Quote hidden}

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