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'[PIC] A couple ICSP questions.'
2008\11\21@131534 by Barry Callahan

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I have a silly and a not-so-silly question, both assume LVP is disabled.

First, the silly question:

When using ICSP to reflash the PIC, all of the timing diagrams show PGC
and PGD being low *before* ~MCLR being brought to VPP. Would you expect
any sort of badness if that weren't the case?

And the not-so-silly question:

When debugging, how does the debugger interrupt the program's execution
in order to read variables, step through the program, etc? Is that done
by throwing ~MCLR to VPP, or through a manipulation of the PGC and PGD
lines?

2008\11\21@170332 by olin piclist

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Barry Callahan wrote:
> When using ICSP to reflash the PIC, all of the timing diagrams show
> PGC and PGD being low *before* ~MCLR being brought to VPP. Would you
> expect any sort of badness if that weren't the case?

Yes, depending on the PIC.

For a general de-mystification of ICSP, see
http://www.embedinc.com/picprg/icsp.htm.

> When debugging, how does the debugger interrupt the program's
> execution in order to read variables, step through the program, etc?
> Is that done by throwing ~MCLR to VPP, or through a manipulation of
> the PGC and PGD lines?

The debugger works on a combination of debug executive running on the target
chip and special hardware tied to the ICSP lines so that the executive can
be run at certain times.


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