Searching \ for '[PIC] 18F4550 does not respond to interrupts at al' in subject line. ()
Make payments with PayPal - it's fast, free and secure! Help us get a faster server
FAQ page: www.piclist.com/techref/microchip/ints.htm?key=interrupt
Search entire site for: '18F4550 does not respond to interrupts at al'.

Exact match. Not showing close matches.
PICList Thread
'[PIC] 18F4550 does not respond to interrupts at al'
2008\07\31@044016 by Wojciech Zabolotny

picon face
In my previous post I complained about EUSART not generating interrupts.
Now I have tested other interrupt, and it appeared that the PIC does not respond
to any interrupt.

I have added:

bsf INTCON,INT0IE, ACCESS

to the initialization routine
and then:

HiIrq:
                       pop ; According to the errata 80220g.pdf
                       banksel int_flag
                       setf int_flag, BANKED
                       call ser_rx_irq
                       call int0_irq
                       retfie FAST

int0_irq:
                       btfss INTCON,INT0IF,ACCESS
                       return
                       bcf   INTCON,INT0IE,ACCESS
                       return

What I can see is that INTCON has initially value 0xd5, and then,
after I press the button connected to the INT0 line - 0xd7.
The HiIrq routine is never called, even though GIE and PEIE bits are
set.
Does it mean, that this chip is damaged? What else could cause such a
problem?
Unfortunately I'm currently on my hollidays and this is the only
18F4550 I have with me :-(

--
Wojtek

2008\07\31@052906 by Tamas Rudnai

face picon face
Hi,

How do you call HiIrq? Where is your ISR? How did you setup IPEN / are you
using interrupt priorities? How did you set up RCIP/TXIP?

Tamas


On Thu, Jul 31, 2008 at 9:39 AM, Wojciech Zabolotny <spam_OUTwzab01TakeThisOuTspamgmail.com>wrote:

{Quote hidden}

> -

2008\07\31@070155 by Wojciech Zabolotny

picon face
Tamas Rudnai wrote:
> How do you call HiIrq? Where is your ISR? How did you setup IPEN / are you
> using interrupt priorities? How did you set up RCIP/TXIP?

The details were described in the previous post:
http://www.piclist.com/techref/postbot.asp?by=time&id=piclist\2008\07\30\130553a&tgt=post

The whole initialization sequence currently is as follows:
       movlw b'11111111'
       movwf TRISC,ACCESS
       movlw low(d'1249')
       movwf SPBRG,ACCESS
       movlw high(d'1249')
       movwf SPBRGH,ACCESS
       movlw b'00100100'
       movwf TXSTA,ACCESS
       movlw b'10000000'
       movwf RCSTA,ACCESS
       movlw b'00001000'
       movwf BAUDCON,ACCESS
       movlw 0x3
       movwf FSR2H
       movlw 0x0
       movwf FSR2L
       bcf PIR1,RCIF,ACCESS
       bsf PIE1,RCIE,ACCESS
       bcf IPR1,RCIP,ACCESS ; bsf - didn't help either...
       bsf RCSTA,CREN,ACCESS
       banksel int_flag
       clrf int_flag, BANKED
       bcf RCON,IPEN,ACCESS
       bsf INTCON,INT0IE, ACCESS
       bsf INTCON,GIE, ACCESS ; GIE enabled
       bsf INTCON,PEIE, ACCESS ; PEIE enabled

; Code at 0x08 (interrupt vector)
       call        HiIrq,FAST
; Code of fast interrupt routine
HiIrq:        pop ; According to the errata 80220g.pdf
       banksel int_flag
       setf int_flag, BANKED
       call ser_rx_irq
       call int0_irq
       retfie FAST

int0_irq:
       btfss INTCON,INT0IF,ACCESS
       return
       bcf   INTCON,INT0IE,ACCESS
       return

ser_rx_irq:
       global ser_rx_irq
       btfss PIR1,RCIF,ACCESS
       return
       movf RCSTA,W,ACCESS
       btfsc RCSTA,FERR,ACCESS
       bra reenable_rx
       btfsc RCSTA,OERR,ACCESS
       bra reenable_rx
       movf RCREG,W,ACCESS
       movwf INDF2,ACCESS ; INDF2 used only for serial buffer
                               ; 256 bytes long
       incf FSR2L,F,ACCESS
       return
reenable_rx:
       bcf RCSTA,CREN,ACCESS
       bsf RCSTA,CREN,ACCESS
       return
--
TIA, Wojtek

PS. Does anybody know how to assure proper threading, when receiving
piclist in the digest mode? I was trying to modify headers by hand to
assure proper threading, but results are very poor. Every message
appears as independent thread causing the mess :-( Sorry!

2008\07\31@082131 by WH Tan

picon face
2008/7/31 Wojciech Zabolotny <.....wzab01KILLspamspam@spam@gmail.com>:

{Quote hidden}

Wojciech,

Check your call stack!  Your ISR actually didn't 'exit' properly.

For example, at vector 0x0008, you should use goto/bra instead.


Best regards,

--
WH Tan

2008\07\31@083556 by Tamas Rudnai

face picon face
> Check your call stack!  Your ISR actually didn't 'exit' properly.
> For example, at vector 0x0008, you should use goto/bra instead.

It is ok I believe actually, take a look at the POP instruction:

> ; Code at 0x08 (interrupt vector)
>        call    HiIrq,FAST
> ; Code of fast interrupt routine
> HiIrq:  pop ; According to the errata 80220g.pdf

The reason Wojciech did the is this way is because there was an issue with
the high priority interrupts so it can corrupt WREG when the interrupt
occurs during the execution of a two cycle instruction that has the target
of WREG. Wojciech was pointing out that errata earlier on.

Tamas


On Thu, Jul 31, 2008 at 1:21 PM, WH Tan <whsiung.myspamKILLspamgmail.com> wrote:

{Quote hidden}

> -

2008\07\31@085045 by Michael Rigby-Jones

picon face

> 2008/7/31 Wojciech Zabolotny <EraseMEwzab01spam_OUTspamTakeThisOuTgmail.com>:
>
> >
> > ; Code at 0x08 (interrupt vector)
> >        call    HiIrq,FAST
> > ; Code of fast interrupt routine
> > HiIrq:  pop ; According to the errata 80220g.pdf
> >        banksel int_flag
> >        setf int_flag, BANKED
> >        call ser_rx_irq
> >        call int0_irq
> >        retfie FAST
> >
> > int0_irq:
>

> {Original Message removed}

2008\07\31@085400 by WH Tan

picon face
2008/7/31 Tamas Rudnai <tamas.rudnaispamspam_OUTgmail.com>:
>
> It is ok I believe actually, take a look at the POP instruction:
>


Oops, my bad.
I missed the POP instruction.

Thanks Tamas.


--
WH Tan

2008\07\31@105315 by WH Tan

picon face
2008/7/31 Wojciech Zabolotny <@spam@wzab01KILLspamspamgmail.com>:

> In my previous post I complained about EUSART not generating interrupts.
> Now I have tested other interrupt, and it appeared that the PIC does not respond
> to any interrupt.
>


Hello Wojtek,

I see you have experienced some problem with PIC interrupt - from
initially USART to now external INT.  Have you considered to
experiment with a timer interrupt instead?  I think a timer is more
easier to set up since it doesn't depend on external event.  And it
much more simple to test it in MPLAB SIM.

Best regards,

--
WH Tan


'[PIC] 18F4550 does not respond to interrupts at al'
2008\08\02@114022 by Wojciech Zabolotny
picon face
WH Tan wrote:

> I see you have experienced some problem with PIC interrupt - from
> initially USART to now external INT.  Have you considered to
> experiment with a timer interrupt instead?  I think a timer is more
> easier to set up since it doesn't depend on external event.  And it
> much more simple to test it in MPLAB SIM.

I have tested my code in MPLAB SIM (under wine), and found it working.

After some googling about PIC and interrupts problems, I have found
the following:
http://www.motherboardpoint.com/t93255-interrupt-not-firing-on-pic18f.html

I checked that in my code (based on the Bradley Minch's USB firmware) I had
the _DEBUG_ON_4L option set. After I replaced it with _DEBUG_OFF_4L,
the interrupts
started to work!

I'm quite surprised, that setting of this option breaks interrupts...
In the datasheet (39632D.pdf) there is nothing about it...
--
Regards, Wojtek

2008\08\02@123450 by Tamas Rudnai

face picon face
Something reminds me to a problem, that is ICD2 reads a register (aka you
are put it into the watch window) then it could ruin things like this. For
example if you read RCREG then RCIF clears, so if you put RCREG into watch
window then it could kill the RCIF flag.

Not sure if i recall te problem well.

Tamas


On Sat, Aug 2, 2008 at 4:39 PM, Wojciech Zabolotny <KILLspamwzab01KILLspamspamgmail.com> wrote:

{Quote hidden}

> -

More... (looser matching)
- Last day of these posts
- In 2008 , 2009 only
- Today
- New search...