Post by thread:[PIC] 12c508a Timing

'[PIC] 12c508a Timing'

I have been searching the datasheet for the 12c5xx  (# DS40139E) and

am probably overlooking it, but cannot seem to find what I am

searching for.

If I am using the internal RC on a 12c508a chip, and assuming that the

OSCCAL register is properly set, what is the frequency tolerance for

the clock?  ie:  4 MHz, +/- what %?

Table 13-3 (page 87) gives some min and max values that work out to

about 9.6% either way, which I assume (HOPE!!!) is the range that

OSCCAL can adjust it either way.  What I cannot find is what the max

variance is based on a properly set OSCCAL.

If this is obviously available, just point out where, and I can search

again from there.

Incidentally, and maybe this is the answer, since the 12c508a uses 6

bits for OSCCAL, and the min and max is 9.6% either way (roughly) for

a total variance of 19.2%,  taking .192 / 63 (bits resolution) gives

me an accuracy of 0.3% (again, roughly).  Does that seem reasonable?

Thanks!

--Joe

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{Quote hidden}> I have been searching the datasheet for the 12c5xx  (# DS40139E) and

> am probably overlooking it, but cannot seem to find what I am

> searching for.

>

> If I am using the internal RC on a 12c508a chip, and assuming that the

> OSCCAL register is properly set, what is the frequency tolerance for

> the clock?  ie:  4 MHz, +/- what %?

>

> Table 13-3 (page 87) gives some min and max values that work out to

> about 9.6% either way, which I assume (HOPE!!!) is the range that

> OSCCAL can adjust it either way.  What I cannot find is what the max

> variance is based on a properly set OSCCAL.

>

> If this is obviously available, just point out where, and I can search

> again from there.

>

> Incidentally, and maybe this is the answer, since the 12c508a uses 6

> bits for OSCCAL, and the min and max is 9.6% either way (roughly) for

> a total variance of 19.2%,  taking .192 / 63 (bits resolution) gives

> me an accuracy of 0.3% (again, roughly).  Does that seem reasonable?

I am afraid I have bad news for you: the specifications for MIN and MAX in

the datasheet are assuming that OSCCAL is set correctly.

Even the newest PICs are not doing real well for accuracy on internal RC.

Also, the RC accuracy seems to be a spec that mChip often ends up having to

loosen up (via an errata) after they actually get some silicon out there. In

other words: take the numbers on a newly announced/released chip with a

grain of salt.

Bob Ammerman

RAm Systems

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It doesn't answer your question, but just thought you may want to know before 

you accidently overwrite it...

You need to read the OSCCAL value within the chip and save the value 

somewhere (for example if it's the ceramic reprogrammable chip, just jot it 

down on the chip itself using a felt marker), or avoid programming over it 

during programming sequence (OTP), since it is set at the factory for the 

"best" value tested at the factory.

On Tuesday 14 September 2004 03:50 pm, Joe Jansen wrote:

> Incidentally, and maybe this is the answer, since the 12c508a uses 6

> bits for OSCCAL, and the min and max is 9.6% either way (roughly) for

> a total variance of 19.2%,  taking .192 / 63 (bits resolution) gives

> me an accuracy of 0.3% (again, roughly).  Does that seem reasonable?

0.3% sounds really nice if you can hold steady the other variables such as 

voltage, current and temperature.   :-)

If we assume that the internal clock is an RC circuit, you may want to lump 

accuracy at about 2 digits, so you may say 4.0MHz, but you do not want to 

say 4.00MHz.

You may want to stick with 4.0+-.05MHz.

A ceramic resonator will get you 3 or 4 digits of accuracy.

A crystal gets you about 5 to 6 digits of accuracy... 4.0000 or 4.00000 mhz

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> I am afraid I have bad news for you: the specifications for MIN and

> MAX in the datasheet are assuming that OSCCAL is set correctly.

> 

> Even the newest PICs are not doing real well for accuracy on

> internal RC

I must say I was disappointed when first booting up a 12F675 with

internal RC. The "nominal" 4MHz turned out to be anything up to

4.3MHz. I plan to use a one-wire data transfer from several 675s

to another micro, and because of the uncertainty an autobaud routine

at the receiver is necessary

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> I must say I was disappointed when first booting up a 12F675 with

> internal RC. The "nominal" 4MHz turned out to be anything up to

> 4.3MHz. I plan to use a one-wire data transfer from several 675s

> to another micro, and because of the uncertainty an autobaud routine

> at the receiver is necessary

You mean Dallas one-wire, or your own protocol? In both cases I think a

10% variation can easily be accomodated.

Wouter van Ooijen

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Van Ooijen Technische Informatica: http://www.voti.nl

consultancy, development, PICmicro products

docent Hogeschool van Utrecht: http://www.voti.nl/hvu

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Jinx <spam_OUTpiclistTakeThisOuTmit.edu> wrote:

> I must say I was disappointed when first booting up a 12F675 with

> internal RC. The "nominal" 4MHz turned out to be anything up to 4.3MHz.

> I plan to use a one-wire data transfer from several 675s to another

> micro, and because of the uncertainty an autobaud routine at the

> receiver is necessary

Depends on the protocol you use.  Manchester encoding (with a decoder 

written intelligently), for instance, can easily tolerate that much 

variation in the clocks of the transmitter and receiver without any 

autobaud calculations... And so could a pulse-width scheme where, 

say, a 0 is a 50-microsecond (nominally) wide pulse, a 1 is a 100-

microsecond-wide pulse, and there's a short gap between each bit.

Or, easier, a scheme where a 0 is an x-microsecond gap followed by a 

2x-microsecond pulse, and a 1 is a 2x-microsecond gap followed by an 

x-microsecond pulse (with a "start pulse" in front of your message, 

of course).

-Andy

=== Andrew Warren - .....aiwKILLspam@spam@cypress.com

=== 

=== Principal Design Engineer

=== Cypress Semiconductor Corporation

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> > I must say I was disappointed when first booting up a 12F675 with

> > internal RC. The "nominal" 4MHz turned out to be anything up to

> > 4.3MHz. I plan to use a one-wire data transfer from several 675s

> > to another micro, and because of the uncertainty an autobaud routine

> > at the receiver is necessary

>

> You mean Dallas one-wire, or your own protocol? In both cases I think a

> 10% variation can easily be accomodated.

>

> Wouter van Ooijen

Dallas one-wire actually accommodates slaves with (almost) -50% to +100%

timing relative to the nominal bit time.

Bob Ammerman

RAm Systems

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Joe Jansen wrote:

> Incidentally, and maybe this is the answer, since the 12c508a uses 6

> bits for OSCCAL, and the min and max is 9.6% either way (roughly) for

> a total variance of 19.2%,  taking .192 / 63 (bits resolution) gives

> me an accuracy of 0.3% (again, roughly).  Does that seem reasonable?

No, that's the adjustment precision, NOT the accuracy.  I sortof remember

these chips having around 5% overall oscillator accuracy with the factory

OSCCAL value.

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 > micro, and because of the uncertainty an autobaud routine at the

> > receiver is necessary

> 

> Depends on the protocol you use.  Manchester encoding

Quite so. I've been playing around with Manchester in another

project and quite honestly I'd not made the obvious connection

to use it in this application too. It's been one of those weeks. As

you say, there are several ways it could be done, none of them

too difficult to achieve reliable transfer with. Autobauding just

requires timing a preamble bit, and it appears to be satisfactory

for the moment. Now that a data transfer has proved the h/w

works (there's not a simple physical connection between the

micros) it could be time to look at some optimisation in the s/w

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On Wed, 15 Sep 2004 08:11:06 -0400, Olin Lathrop

<olin_piclistKILLspamembedinc.com> wrote:

> 

> No, that's the adjustment precision, NOT the accuracy.  I sortof remember

> these chips having around 5% overall oscillator accuracy with the factory

> OSCCAL value.

Is the 5% based on experience, or is it documented somewhere?

Hrm..  So I can control precisely where the frequency wanders around? 

<sarcasm>  That's handy...  </sarcasm>

Since the 10F chips are internal oscillator only, are they any better

at holding a frequency?  Anybody with some of these looked into this

at all?  Table 12-4 claims 1%, but Temp and Vdd are TBD.

Thanks for all the feedback.  Not exactly what I had hoped to hear, tho...  <G>

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On Sep 16, 2004, at 5:32 AM, Joe Jansen wrote:

> So I can control precisely where the frequency wanders around?

> <sarcasm>  That's handy...  </sarcasm>

>

Why, yes it is.  See the ATtiny11 for a different scheme. :-(

And frequency will be dependent on things like temp and supply

voltage, which can be controlled to some extent, so the freq

may not be as variable as the spec sheet (must) imply.

> Since the 10F chips are internal oscillator only, are they any

> better at holding a frequency?

>

I think so.  The 10F claims a 'precision' internal clock, like the

12f675, which is distinct from the simple 4MHz oscillator of the 12c508.

I think microchip got a message that people wanted the internal clock

to be good enough to do rs232...

BillW

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At 10:30 AM 9/16/2004, William "Chops" Westfield wrote:

>On Sep 16, 2004, at 5:32 AM, Joe Jansen wrote:

>

>>So I can control precisely where the frequency wanders around?

>><sarcasm>  That's handy...  </sarcasm>

>Why, yes it is.  See the ATtiny11 for a different scheme. :-(

To be fair, the tiny11's scheme is atypical of the AVR line.

AFAIK, all the others have an Osccal register, and you can calibrate the internal osc.

>And frequency will be dependent on things like temp and supply

>voltage, which can be controlled to some extent, so the freq

>may not be as variable as the spec sheet (must) imply.

One would hope that the spec sheets always show the guaranteed limits.

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