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PICList Thread
'[PIC]:x14 program blk vs x12 program blk'
2002\04\10@052625 by Keong

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Hi

I notice that the program memory for the PIC12CE518 is
organised in 512x12 blocks, rather than the normal x14
blocks. Is there any difference in its usage as
compared to those using x14 block program space or are
there any particular steps that I need to take into
account when writing the program for the chip that is
using 12 bits per program memory space (PIC12CE518).

Thanx

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2002\04\10@075721 by Mark J. Dulcey

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Keong wrote:
> Hi
>
> I notice that the program memory for the PIC12CE518 is
> organised in 512x12 blocks, rather than the normal x14
> blocks. Is there any difference in its usage as
> compared to those using x14 block program space or are
> there any particular steps that I need to take into
> account when writing the program for the chip that is
> using 12 bits per program memory space (PIC12CE518).

The 512 word blocks are "normal" for all the low-end PICs - the 12C
series and the 16C5x. (I wouldn't bother with the 16C5x series for any
new designs, though; use a mid-range PIC instead. The price difference
is negligible.) Since the 12CE518 only has 512 words of program memory,
you don't need to worry about any interpage issues on that processor.
Just in case you try some of the low-end chips with more program memory,
though...

If your program is 512 bytes or less, there isn't anything special you
will need to do. If it's larger, you have to deal with interpage jumps.
They're handled differently than on the mid-range PICs. There is no
PCLATH register; instead, you use bits PA0 and PA1 of the status register.

CALL instructions only have 8 address bits, so they can't access the
second half of a memory page. Therefore, you have to put subroutines in
the first half of each page.

Another difference is access to registers. There are only five bits of
address for registers in the 12-bit instructions, so you can only see 32
at a time; rather than the RP0 and RP1 bits of the status register, you
use the FSR register.

Remember those TRIS and OPTION instructions that Microchip keeps trying
to convince you not to use? Well, on the low-end chips, you MUST use
them; they're the only way to get at the TRIS and OPTION registers.

Other differences: the reset vector goes to the highest memory location,
not address 0. (One simple way to work around that is to put a NOP at
the top of memory, and pretend that the reset goes to address 0 as
usual.) There are no addlw and sublw instructions.

Finally, if you're using a part with a built-in oscillator, don't forget
to save the calibration value, and write it with your program code! (The
16F628 makes life so much easier that way, with the calibration info
safely hidden from users. Or maybe they just found a way to get rid of
enough process variation that they don't need one any more.)

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2002\04\10@090113 by Alan B. Pearce

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>Other differences: the reset vector goes to the highest memory location,
>not address 0. (One simple way to work around that is to put a NOP at
>the top of memory, and pretend that the reset goes to address 0 as
>usual.) There are no addlw and sublw instructions.

>Finally, if you're using a part with a built-in oscillator, don't forget
>to save the calibration value, and write it with your program code! (The
>16F628 makes life so much easier that way, with the calibration info
>safely hidden from users. Or maybe they just found a way to get rid of
>enough process variation that they don't need one any more.)

Do not forget that the highest program memory address is usually the OSCCAL
value included with an instruction, so do not overwrite it with a NOP.

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'[PIC]:x14 program blk vs x12 program blk'
2002\07\02@165224 by Dwayne Reid
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At 02:23 AM 4/10/02 -0700, Keong wrote:
>Hi
>
>I notice that the program memory for the PIC12CE518 is
>organised in 512x12 blocks, rather than the normal x14
>blocks. Is there any difference in its usage as
>compared to those using x14 block program space or are
>there any particular steps that I need to take into
>account when writing the program for the chip that is
>using 12 bits per program memory space (PIC12CE518).

Yes - there are several important differences.  I'll highlight a few of
those here but you *REALLY* have to read the data sheet to avoid being burned.

1) 12 bit core does not have "addlw" or "sublw" instructions

2) RAM banks are 32 bytes instead of 128 bytes

3) ROM pages are 512 bytes instead of 2K bytes.

4) The entry points for all subroutines must be within the first 256 bytes
of a ROM page.  All lookup tables must reside entirely within the same 256
byte space.  In essence, anything that modifies PCL has to live within
first half of any ROM page.

5) No TRIS registers.  You have to use the TRIS n instruction
instead.  Note that this is a write only instruction - you cannot read the
contents of the TRIS registers.

6) same for the OPTION register: use the OPTION instruction to load this
write-only register.

I'm sure that there are other things that I have missed but this is what
comes to mind right now.

dwayne

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2002\07\02@235751 by Jim Robertson

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{Quote hidden}

Two level stack (Except for 16HV540 as it has 3 or 4 levels, can't remember.)
No Return instruction (only Retlw)
No interrupts.
Different Reset vector.

-Jim




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2002\07\03@185526 by Dwayne Reid

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At 01:57 PM 7/3/02 +1000, Jim Robertson wrote:

{Quote hidden}

Thanks, Jim.  I think that you got all the 'gotchas' that I missed.

dwayne

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