Post by thread:[PIC]:Is it possible to adjust internal osc to 3.6

For short messages I think it should be possible to implement simple, low speed (1200/2400) RS-232 in chips that have an internal 4MHz (nominal) oscillator *IF* the osccal can be loaded with a correctly calculated value. At these low speeds it should be possible to identify and synchronise with a start bit and then read in a few bytes before losing synchronisation. If messages are restricted to that size comms should be possible. Does anyone know if osccal can be adjusted to slow the chip down by about 8% (((4-3.6864)/4)*100) ? If it can, what is the formula to calculate the osccal value from the factory supplied osccal adjustment value ? If it can't what is the formula to 'drop' cycles to simulate 3.6864MHz when the chip is operating at 4MHz ? (nop every 12.5 instructions ?) Thanx in advance. Bye. -- http://www.piclist.com#nomail Going offline? Don't AutoReply us! email spam_OUTlistservTakeThisOuTmitvma.mit.edu with SET PICList DIGEST in the body

How about making a small program that simply changes the OSCCAL value when you depress a button. Each button press could decrease the value by 1 (or whatever) and measure the CLKOUT until you get 3.686 or whatever you want. Then by knowing how many button presses it took, define that value for the OSCCAL and reload it. --Andrew _________________________________________________________________ Get your FREE download of MSN Explorer at http://explorer.msn.com/intl.asp -- http://www.piclist.com#nomail Going offline? Don't AutoReply us! email .....listservKILLspam@spam@mitvma.mit.edu with SET PICList DIGEST in the body

Serial comms with 1 start bit, eight data bits, and one stop bit aren't that fussy about timing. It automatically resynchronizes at every stop bit/ start bit transition, so the message length doesn't matter. In theory you could be off by 10% and it would still work. The character length matters, so if you use 2 stop bits or fewer data bits the timing is even more forgiving. In practice I wouldn't drift farther than +/-5% worst case, +/-3% is better. Are you using a hardware or software UART? Sherpa Doug > {Original Message removed}

Scott recently was talking about accumulator registers...maybe that would do the trick for you. Josh "Gennette, Bruce" wrote: {Quote hidden}> > For short messages I think it should be possible to implement simple, low > speed (1200/2400) RS-232 in chips that have an internal 4MHz (nominal) > oscillator *IF* the osccal can be loaded with a correctly calculated value. > At these low speeds it should be possible to identify and synchronise with a > start bit and then read in a few bytes before losing synchronisation. If > messages are restricted to that size comms should be possible. > > Does anyone know if osccal can be adjusted to slow the chip down by about 8% > (((4-3.6864)/4)*100) ? > > If it can, what is the formula to calculate the osccal value from the > factory supplied osccal adjustment value ? > > If it can't what is the formula to 'drop' cycles to simulate 3.6864MHz when > the chip is operating at 4MHz ? (nop every 12.5 instructions ?) > > Thanx in advance. > Bye. > > -- > http://www.piclist.com#nomail Going offline? Don't AutoReply us! > email listservKILLspammitvma.mit.edu with SET PICList DIGEST in the body -- A common mistake that people make when trying to design something completely foolproof is to underestimate the ingenuity of complete fools. -Douglas Adams -- http://www.piclist.com#nomail Going offline? Don't AutoReply us! email .....listservKILLspam.....mitvma.mit.edu with SET PICList DIGEST in the body

You don't need to mess with oscal, nor use a specific clock, assuming you're using bit-bashed RS232. It is not particularly difficult to auto-detect the baudrate of an incoming signal, as long as you know what initial character you are expecting (a zero byte is best, as it has maximal length), and then adjust the timing of your tx/rx code to compensate. On Thu, 6 Dec 2001 16:15:04 +1100, you wrote: {Quote hidden}>For short messages I think it should be possible to implement simple, low >speed (1200/2400) RS-232 in chips that have an internal 4MHz (nominal) >oscillator *IF* the osccal can be loaded with a correctly calculated value. >At these low speeds it should be possible to identify and synchronise with a >start bit and then read in a few bytes before losing synchronisation. If >messages are restricted to that size comms should be possible. > >Does anyone know if osccal can be adjusted to slow the chip down by about 8% >(((4-3.6864)/4)*100) ? > >If it can, what is the formula to calculate the osccal value from the >factory supplied osccal adjustment value ? > >If it can't what is the formula to 'drop' cycles to simulate 3.6864MHz when >the chip is operating at 4MHz ? (nop every 12.5 instructions ?) > >Thanx in advance. >Bye. -- http://www.piclist.com#nomail Going offline? Don't AutoReply us! email EraseMElistservspam_OUTTakeThisOuTmitvma.mit.edu with SET PICList DIGEST in the body