> > Why is the INTF flag set if I dit not enable the INTE?
>
> The flag will be set whether INTE is set or not. But no interrupt
> will be generated if INTE=0. When TMR0 causes an interrupt
> and the ISR is entered, an event on the external INT pin may
> have already happened (but it did not cause the IRQ as INTE
> is clear) which set INTF. That's why you need to test both INTF
> and INTE for 1. If INTF AND INTE are 1 and T0IF=0 then you
> know the IRQ was from the external event. If all the test bits
> are 1 (T0IF, INTE, INTF) then you'll have to decide which IRQ
> to process first. You say you want TMR0 to take priority, so
> deal with that. You don't say if the external event is transitory
> (or lasts longer than the TMR0 period), so maybe you could
> also test the INT pin for level after processing the TMR0 IRQ
> to look for a valid EXT INT event
>
> Other micros have vectors set aside for the various IRQ sources
> which makes it easier to separate IRQs and have different
> ISRs for them so the sort of testing we're talking about here
> doesn't need to be done
>
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>