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'[PIC]: maths for parsing value to delay'
2002\06\12@114401 by Jonathan Starr

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This damn project seems to be more trouble than it's worth, if anyone mathematically minded can help me with this I would be very grateful.

Okay, I have a ADC input that has full range (ie. 0 to 255) and basically it needs to cause a delay like this:

ADC_VAL                Delay in cycles

0                              400
255                          3200

So this really means that each decimal '1' of ADC_VAL equates to 11 cycles extra delay, ok so its not exactly 11 but it'll do, it'll only be 5 cycles off at the end.
Now here comes the part that is giving me grief, I can do 3205 cycles with a two tier nested delay, but there are two values that affect the delay time, the inner and outer loop variables.
I think the way to do it would be too divide the required delay into 255 to get a carry (whole numbers) and the rest would go into the inner loop ie. the stuff after the decimal point to 3 sig figs.

This would be all well and good except for the fact that Nikolai Golovchenko's division code uses a whopping great 400 cycles.
I can't think of anything I can do, as I require two values I can't even do a computed jump into a 255 long retlw table.

Is anyone able to give me a poke towards a solution?

Jonathan Starr

R&D Technician
Electronix Limited

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2002\06\12@124417 by Brendan Moran

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Ok, I have a possible solution for you.  As long as 11 cycles per increment
is OK for you, and you don't need the extra precision, I can see a way of
doing this.

1: Forget division.  If you have time critical code that requires division,
a RISC processor is the wrong solution.

2: Remember that you can implement a 0-255 counter.

Here's what you can do:  take the value from the ADC, and throw it in some
working register for the sake of argument,  call it counter.  Then use a
nested loop structure where the internal loop is an 11 cycle delay (make it
a bit less so that the cycles in the outer loop make it 11 cycles (this
counter can be done in W)  then loop through that delay 0-255 times (dec
counter each time until you hit 0), giving you your 0-2805 cycle delay, then
you add an external 400 cycle delay.

I think that should do it.

I had a problem a lot like that on one of my midterms or finals once...

--Brendan

{Original Message removed}

2002\06\12@134946 by Scott Dattalo

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On Wed, 12 Jun 2002, Jonathan Starr wrote:

> This damn project seems to be more trouble than it's worth, if anyone mathematically minded can help me with this I would be very grateful.
>
> Okay, I have a ADC input that has full range (ie. 0 to 255) and basically it needs to cause a delay like this:
>
> ADC_VAL                Delay in cycles
>
> 0                              400
> 255                          3200
>
> So this really means that each decimal '1' of ADC_VAL equates to 11
> cycles extra delay, ok so its not exactly 11 but it'll do, it'll only be
> 5 cycles off at the end.
>
> Now here comes the part that is giving me grief, I can do 3205 cycles
> with a two tier nested delay, but there are two values that affect the
> delay time, the inner and outer loop variables. I think the way to do it
> would be too divide the required delay into 255 to get a carry (whole
> numbers) and the rest would go into the inner loop ie. the stuff after
> the decimal point to 3 sig figs.

Why bother with a nested loop? If you need 11 cycles per adc count, then
write a loop that will execute 11 cycles for each iteration:

Loop_11cycles:

    goto     $+1   ;0,1
    goto     $+1   ;2,3
    goto     $+1   ;4,5
    goto     $+1   ;6,7

    decfsz   counter,f      ;8
     goto    Loop_11cycles  ;9,10


Scott

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