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'[PIC]: Stupid newbie PIC question'
2003\02\16@185445 by Neil Bradley

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Sorry for the potential double post (I mistyped the subject prefix):

Today is the first day of programming the PIC for me, so forgive me if I'm
asking something that's stupid or has been answered a zillion times. I
have checked over the various bits of documentation and examples I've
found and according to what's going on, the code isn't setting the
TRISA/B/C ports as they should!

I'm using MPLAB version 6.10.0.0 with an 18F252, and here's my code
snippet:

       movlw   PORTA_IN        ; Get port A's input setting
       movwf   TRISA           ; Set up appropriate tristating

; Now port B

       movlw   PORTB_IN        ; Get port B's input setting
       movwf   TRISB           ; Set up appropriate tristating

; Now port C

       movlw   PORTC_IN        ; Get port C's input setting
       movwf   TRISC           ; Set up appropriate tristating

PORTA_IN = 0x40
PORTB_IN = 0x01
PORTC_IN = 0xb8

I have verified that W is getting loaded with the values above (through
the IDE/debugger). When I read the tristate registers for each port, I get
this:

TRISA = 0x00
TRISB = 0x81
TRISC = 0xB8

The TRISA/B/C ports *ARE* changing, but TRISA/TRISB aren't coming up with
the right values. Any idea what I'm doing wrong? Thanks in advance!

-->Neil

-------------------------------------------------------------------------------
Neil Bradley            In the land of the blind, the one eyed man is not
Synthcom Systems, Inc.  king - he's a prisoner.
ICQ #29402898

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2003\02\16@195629 by Dave Dilatush

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Neil,

Seems to me the code you showed should work.  Are you sure you're
defining all the register locations correctly by including a

 #include <P18F252.INC>

statement at the start of your code?

Dave D.

Neil Bradley wrote...

{Quote hidden}

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2003\02\16@201752 by David Duffy

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Neil wrote:
{Quote hidden}

I've not looked at the 18Fxx but the TRIS registers are in bank 1 normally
so you'll have to do something like this:

bsf             rp0             ;select register bank 1
movlw           0x81            ;get the setting
movwf           trisc           ;copy it to the tris register
bcf             rp0             ;back to register bank 0

The ports themselves (in bank 0) are the same address as the tris
registers, only up in register bank 1. It's an easy mistake to make.
David...
___________________________________________
David Duffy        Audio Visual Devices P/L
U8, 9-11 Trade St, Cleveland 4163 Australia
Ph: +61 7 38210362   Fax: +61 7 38210281
New Web: http://www.audiovisualdevices.com.au
___________________________________________

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2003\02\16@205334 by Dave Dilatush

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David Duffy wrote...

>I've not looked at the 18Fxx but the TRIS registers are in bank 1 normally
>so you'll have to do something like this:
>
>bsf             rp0             ;select register bank 1
>movlw           0x81            ;get the setting
>movwf           trisc           ;copy it to the tris register
>bcf             rp0             ;back to register bank 0
>
>The ports themselves (in bank 0) are the same address as the tris
>registers, only up in register bank 1. It's an easy mistake to make.

Not for the PIC18 series.  With these chips you no longer need
bother with bank bits when accessing SFRs: they're all in the
"access bank" space and are always visible regardless of the
current bank selection.

DD

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2003\02\16@210431 by Daniel Imfeld

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The PIC18 actually differs from the PIC16 series in this respect.  It
keeps all the SFRs (TRISx included) at the end of memory, and
instructions can use the "access bank," a flag in instructions that
allows you access to the first 128 bytes of Bank 0 and the last 128
bytes of Bank 15 where the SFRs reside.  So, you don't need to change
the bank registers every time you want to access the SFRs.  Stilll, this
might be something good to check.  Depending on how the constants are
defined, MPASM can automatically determine whether to use the access
bank or to address using the bank register.  Here's a snippet from the
18F252 header:
TRISC           EQU  H'0F94'
TRISB           EQU  H'0F93'
TRISA           EQU  H'0F92'
Because they are defined using absolute addressing instead of just
H'94', for example, MPASM automatically uses the access bank when
referencing these registers.

Anyway, I played around in MPLAB a bit, and I think the problem is that
the simulator is using one of the clock options in which RA6 is clock
output.  If you change PORTA_IN to 0x20, it works, so you just have to
make sure it's in a mode where RA6 is a normal I/O pin.  I was unable to
reproduce the problems with TRISB being set to 0x81 though.   That
worked fine when I tried it.

Daniel Imfeld

{Original Message removed}

2003\02\16@212006 by David Duffy

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> >I've not looked at the 18Fxx but the TRIS registers are in bank 1 normally
> >so you'll have to do something like this:
> >
> >bsf             rp0             ;select register bank 1
> >movlw           0x81            ;get the setting
> >movwf           trisc           ;copy it to the tris register
> >bcf             rp0             ;back to register bank 0
> >
> >The ports themselves (in bank 0) are the same address as the tris
> >registers, only up in register bank 1. It's an easy mistake to make.

Dave Dilatush:
>Not for the PIC18 series.  With these chips you no longer need
>bother with bank bits when accessing SFRs: they're all in the
>"access bank" space and are always visible regardless of the
>current bank selection.

Cool - I hate the register banks. Gonna have to get some 18Fxx
devices to play with soon I think.
David...
___________________________________________
David Duffy        Audio Visual Devices P/L
U8, 9-11 Trade St, Cleveland 4163 Australia
Ph: +61 7 38210362   Fax: +61 7 38210281
New Web: http://www.audiovisualdevices.com.au
___________________________________________

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2003\02\16@215822 by Dave Dilatush

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David Duffy wrote...

>Cool - I hate the register banks. Gonna have to get some 18Fxx
>devices to play with soon I think.

No program memory paging, either.  Multiple FSR/INDF registers.
No more retlw tables.  40 MHz speed.

Sweet stuff, I tell you.

DD

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2003\02\16@221941 by David Duffy

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>David Duffy wrote...
> >Cool - I hate the register banks. Gonna have to get some 18Fxx
> >devices to play with soon I think.

Dave Dilatush wrote:
>No program memory paging, either.  Multiple FSR/INDF registers.
>No more retlw tables.  40 MHz speed.

Stop it, you're making me drool !  [runs off to get some 18Fxx pdf's]
They'll be just the ticket for some DMX projects I'm doing soon.
David...
___________________________________________
David Duffy        Audio Visual Devices P/L
U8, 9-11 Trade St, Cleveland 4163 Australia
Ph: +61 7 38210362   Fax: +61 7 38210281
New Web: http://www.audiovisualdevices.com.au
___________________________________________

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2003\02\16@223025 by Ned Konz

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On Sunday 16 February 2003 06:54 pm, Dave Dilatush wrote:
> David Duffy wrote...
>
> >Cool - I hate the register banks. Gonna have to get some 18Fxx
> >devices to play with soon I think.
>
> No program memory paging, either.  Multiple FSR/INDF registers.
> No more retlw tables.  40 MHz speed.

And a bug with calling across the 0x4000 boundary, too (that I just
heard about) (see the PIC18FXX2 Rev. B3/B4 Silicon/Data Sheet
Errata). Work-arounds exist, though:
---------
Two possible solutions are presented. Others may exist. It is
recommended to implement either or both as needed. 1. Insert a data
word of value FFFFh as the first instruction in the destination of a
CALL or GOTO. 2. Insert a data word of value FFFFh immediately
following any RETURN, RETLW, or RETFIE instruction.
---------

However, I don't know whether any of the compilers I have (the CCS PCH
and Microchip C18) deal with this problem.

Still, they *are* nice chips compared to the 14-bitters.

You can also read the top of stack (!).

Note that there *is* still RAM banking.

It's hard to justify using a 16F877 (for instance) when you can get an
18F442 (with twice the RAM and program space) for less money.

--
Ned Konz
http://bike-nomad.com
GPG key ID: BEEA7EFE

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2003\02\16@225409 by Dave Dilatush

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David Duffy wrote...

>Stop it, you're making me drool !  [runs off to get some 18Fxx pdf's]
>They'll be just the ticket for some DMX projects I'm doing soon.

Oh, and I forgot: real branch-on-condition instructions, and a
hardware multiply.  And automatic context-save and restore for
interrupts.

The PIC18Fxx2's are nice.

Drool on...

DD

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2003\02\17@010602 by Thomas C. Sefranek

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Dave,

The beauty of the 18 series is... NO BANKING WORRIES.

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> {Original Message removed}

2003\02\17@043858 by Wouter van Ooijen

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> The PIC18 actually differs from the PIC16 series in this respect.  It
> keeps all the SFRs (TRISx included) at the end of memory, and
> instructions can use the "access bank,"

Make that 'most SFRs': the 18Fxx8 series (with CAN) have the CAN SFRs
outside the access bank, so back to bank switching! But if you use CAN
you will probably use a compiler that takes care of this uglyness.

Wouter van Ooijen

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2003\02\17@104236 by Olin Lathrop

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> I've not looked at the 18Fxx but the TRIS registers are in bank 1
normally
> so you'll have to do something like this:
>
> bsf             rp0             ;select register bank 1
> movlw           0x81            ;get the setting
> movwf           trisc           ;copy it to the tris register
> bcf             rp0             ;back to register bank 0
>
> The ports themselves (in bank 0) are the same address as the tris
> registers, only up in register bank 1. It's an easy mistake to make.

This doesn't apply to the PIC18 series.  They have a totally different RAM
address space model.  The RP0 and RP1 bits don't exist.  Instead there is
the BSR register and the "access bank".  See the manual for details.


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