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'[PIC]: SPI continuous transmission'
2001\05\25@041021 by Harald Milz

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Hi,

I need to sent 5 Mbps straight from a PIC. The SSP module should be able to
do just that provided I can send continuous. Since SPI is a synchronous
interface there is no start/stop bit. How can I make sure the data is
received correctly when SCK never stops, and bits are shifted without
pause? I read several Microchip docs but they did not enlighten me so
far...

THX...

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2001\05\25@055743 by Thomas C. Sefranek

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Harald Milz wrote:

> Hi,
>
> I need to sent 5 Mbps straight from a PIC.

WHICH PIC?
Most can not do that rate.

My 18C452s can do that RATE but not continuous.
AT 40 MHz (PLL) Clock rate that is.
That leaves you 16 machine cycles to do all the processes of I/O
between bytes. If you have a really simple parallel to serial job,
you probably can do this, but it's a HUGH waste of a good chip
to make it into a shift register.

> The SSP module should be able to
> do just that provided I can send continuous.

> Since SPI is a synchronous interface there is no start/stop bit.

> How can I make sure the data is received correctly when SCK never stops,

> and bits are shifted without pause?

How do you "make sure the data is received correctly" WITH a start/stop bit?

{Quote hidden}

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2001\05\25@090540 by Olin Lathrop

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> I need to sent 5 Mbps straight from a PIC. The SSP module should be able
to
> do just that provided I can send continuous. Since SPI is a synchronous
> interface there is no start/stop bit. How can I make sure the data is
> received correctly when SCK never stops, and bits are shifted without
> pause? I read several Microchip docs but they did not enlighten me so
> far...

Yes, in theory SPI is just a continuous bit stream.  That why in practise
the master usually controls chip select lines to each of the slaves.  The
slaves ignore bits while chip select is deasserted, and synchronize to the
start of bytes on the leading edge of chip select.  I think you will get
yourself into big trouble if you don't have some way of initially and
periodically synchronizing the receivers to start of bytes.


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Olin Lathrop, embedded systems consultant in Littleton Massachusetts
(978) 742-9014, @spam@olinKILLspamspamembedinc.com, http://www.embedinc.com

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2001\05\30@114010 by Harald Milz

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In article <RemoveME3B0E2BFD.F5BFFFE9TakeThisOuTspamcmcorp.com>, Thomas C. Sefranek <spamBeGonetcsspamBeGonespamcmcorp.com> wrote:
> Harald Milz wrote:
>> I need to sent 5 Mbps straight from a PIC.

> WHICH PIC?

18F232

> My 18C452s can do that RATE but not continuous.
> AT 40 MHz (PLL) Clock rate that is.

From the docs I understood if I write to SSPBUF in time (after exactly 16
cycles) the next transfer should start just when the recent one is done.
Wrong?

> you probably can do this, but it's a HUGH waste of a good chip
> to make it into a shift register.

If it hadn't other tasks too. It needs to set up some audio ADCs as well.

>> How can I make sure the data is received correctly when SCK never stops,
>> and bits are shifted without pause?

> How do you "make sure the data is received correctly" WITH a start/stop bit?

At least the receiver can distinguish the received data words but that
requires a short pause between the stop and start bits.

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