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'[PIC]: SIMM interfacing?'
2001\02\21@164730 by Drew Vassallo

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I'm sure it's possible, but is it practical to interface to a SIMM memory
module for lots of (fast) memory?  I haven't thought about it at all, so
don't blast me... I'm just writing this as I'm thinking about it.

Using a 4MB module could be fun!  As opposed to a 256K-bit I^2C chip.  Maybe
you'd need an SX to really take advantage of the speed, but is it an option?

--Andrew
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2001\02\22@051728 by Simon Nield

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drew:
>I'm sure it's possible, but is it practical to interface to a SIMM memory
>module for lots of (fast) memory?  I haven't thought about it at all, so

I noticed this the other day: http://www.piclist.com/techref/microchip/picsimm.htm

You might find that SODIMMs are worth looking at too (32 or 36 bit wide data i think) if you are
thinking of making a commercial product, as SIMM prices are pretty steep compared with SDRAM
(probably because simms use older non-synchronous dram chips which fewer companies are making
nowdays). Standard DIMMs are probably out as they are 64 bit I think, which probably means too much
extra circuitry to make it worthwhile.

Regards,
Simon

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2001\02\22@180407 by Brandon, Tom

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I could be wrong but:
About the best write you could do is 3 cycles (Write Addr, Write Data, Do
Operation) and I guess 3 for read (Write Addr, Do Operation, Read Data). On
a 20MHz PIC that 3x 50 ns = 150ns, or on a 50MHz scenix 60ns. For reading
you'd need <50ns (PIC) or <20ns (SX) or for multiple writes.

Cypress have 512Kx8 (4M) SRAM down to 12ns which should give 3 (or 4) cycle
read or write with appropriate pin organisation. I guess on a 75 or 100MHz
SX or with external hardware  (e.g. external support for incrementing
address after each byte could allow you to use the PSP at higher speeds) onw
might be able to go faster but not much.

Tom.
{Original Message removed}

2001\02\23@050604 by Simon Nield

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tom:
>About the best write you could do is 3 cycles (Write Addr, Write Data, Do
>...Cypress have 512Kx8 (4M) SRAM down to 12ns which should give 3 (or 4) cycle

if you use sdram then you can get do burst reads / writes which reduces the overhead of setting up
the address conciderably, which is another good reason to look at using more modern ram parts... you
set up the address and then read / write a number of bytes in one burst.

sram is great for true random access at high speed and is easy to control, but is much more
expensive per MB than dram. if one can arrange for data to be accessed in a less random fashion such
that reading / writing a number of contiguous bytes is no problem then synchronous dram is probably
the way to go.

Regards,
Simon

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2001\02\23@081614 by Drew Vassallo

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>I could be wrong but:
>About the best write you could do is 3 cycles (Write Addr, Write Data, Do
>Operation) and I guess 3 for read (Write Addr, Do Operation, Read Data). On
>a 20MHz PIC that 3x 50 ns = 150ns, or on a 50MHz scenix 60ns. For reading
>you'd need <50ns (PIC) or <20ns (SX) or for multiple writes.

SX running at 50MHz is 20ns cycle time.  20MHz PIC is 200ns.

Other than that, I'm still not sure why it's not possible.

--Andrew
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2001\02\23@085436 by Drew Vassallo

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One application for using these higher capacity memory devices would be
long-term or high-speed data logging.  I'd like to be able to store around
4K bytes or more right now for an application, but I have to be able to do
it faster than ~20-50KHz.  Should be no problem for SDRAM or similar, or
even directly to magnetic media.  Any info on this anywhere?  The PICLIST
archives seem a little thin in this area.

--Andrew
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2001\02\23@093235 by Simon Nield

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andrew;
>it faster than ~20-50KHz.  Should be no problem for SDRAM or similar, or
>even directly to magnetic media.  Any info on this anywhere?  The PICLIST

the datasheets for the sdram chips is a good place to start. i strongly suggest you get more than
one manufacturer's datasheet - you can use one to decipher the obscure sections of the other. iirc
hitachi's datasheets were quite readable. don't get put off by the state diagram - you'll probably
only need a tiny subset of those states! use auto precharge mode to make refreshing a lot easier,
then just chuck in a refresh command now and again.
http://www.hitachi-eu.com/hel/ecg/products/memory/struktur/fr_c_d_s.htm

ram modules are then just a handful of these devices (usually 8 bit wide rams, sometimes 4 bits
wide) wired up to give a wide data bus, with a little serial eprom on board to tell you what they
are:
http://www.micron.com/products/datasheets/modds.html#144pin%20DIMM

...looks like sodimms have just as wide a data bus as ordinary dimms btw, pity as it might have been
handy. this probably means you be running the sdrams with a burst length of 1 to avoid too much
external logic.

finding a neat way to wire the whole lot up will be an interesting task.


if you do head down the sdram route and run into difficulties then i may be able to help - i have a
reasonable amount of experience with controlling sdram.

Regards,
Simon

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2001\02\23@095122 by Simon Nield

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me:
>finding a neat way to wire the whole lot up will be an interesting task.

thinking about it a bit further (and looking at the datasheet for a sodimm rather than just guessing
:o) )
you may just be able to get away with wiring all the bytes of the databus in parallel and using a 1
of 8 decoder on the dqms to decide which byte is on the bus... if the decoder is controlled by a
counter which is in turn controlled by the pic (as in reset or allowed to run) then you could even
do an 8 byte read / write burst. the data would be written "diagonally" across the memory, which may
require a bit of care at the ends of a row, but nothing too tricky.

Regards,
Simon

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