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PICList Thread
'[PIC]: Phase of internal TMR0 clocking'
2000\06\03@005112 by Nikolai Golovchenko

---- Original Message ----
From: Dmitry Kiryashov
Sent: Friday, June 02, 2000 16:31:18
Subj: Phase of internal TMR0 clocking

> Hi guys.

> As it was described in many PIC datasheets (notes A below) two cycles are required
> (fetch and execute cycles) to complete any PIC instruction. In fetch cycle PC is
> incremented, then instruction is latched. Then in the execution cycle, data memory
> is read during Q2 (operand read) and written during Q4 (destination write)

Hi Dmitry. Just a little correction (you know it): besides fetch and
execution an instruction may require also a dummy cycle. So for a goto
it would be fetch goto-execute previous instruction-fetch next
instruction after goto-execute goto-fetch instruction pointed by
goto-execute nothing-

It looks from the datasheets that read happens in the beginning
of Q2 (on rising edge of Q2) and write - in the beginning of Q4. Since
all file registers in PIC are probably the same, this should apply to
any file register.

> What internal phase (Q1 Q2 Q3 Q4 ???) TMR0 is incremented every cycle. Is it happened
> in every Q1 (simultaneously with PC increment) or there is another reason to do it
> during other phases of clocking ?

See Fig. 6-4 in F84 datasheet. It increments on Q4 phase.
BTW, Fig. 6-3 has a little mistake - there is an arrow pointing at Q2
beginning and a note "Write TMR0 executed", but the graph shows that
TMR0 write is executed at the beginning of Q4.

> Another question: I still can't understand what was the real reason to introduce
> 2 clocks delay in TMR0 increment after loading TMR0 with new value.

I wish I knew.

> If someone have discovered those questions and have precise answers please do not
> hesitate to share it. Couple of good hints are enough ;)

My answers are certainly not precise, but they don't seem to
contradict the datasheet :).

{Quote hidden}


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