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Thread
'[PIC]: PIC programmer puzzle'
2004\02\08@175826
by
Olin Lathrop
Here is a purely academic puzzle, as I've already found a solution.
I recently made a version of my PIC programmer that is intended to be built
by hand by hobbyists. At the same time, I added labeled pads for the 5
programming signals and an RJ-12 connector so that it could program PICs in
circuit just like an ICD-2. I finally got around to testing the RJ-12 part
this weekend and ran into a interesting problem.
As a quick test I connected the RJ-12 to a few boards that had PICs on them
and that worked with an ICD-2. My programmer failed to read the correct ID
and couldn't program the PICs. This led to a rather lengthy investigation
where I set up a breadboard with just a target PIC connected to the 5 lines
from the RJ-12. It consistantly failed when the PIC was plugged into the
breadboard, but worked when the PIC was plugged into the ZIF socket on the
programmer even though all the connections to the breadboard were still
there. The breadboard and the ZIF socket were essentially wired in parallel
in that case. The right signals were getting to the PIC when it was on the
breadboard as verified by looking at the signals right at the PIC pins with
a scope. These same signals were still wiggling correctly at the breadboard
when the target PIC was in the ZIF socket instead of the breadboard. The
RJ-12 cable came with an ICD-2 (and works correctly with it) and is about 14
inches long. My RJ-12 pigtail adapter to the breadboard is about 6 inches
long, for a total of 20 inches of wire between the RJ-12 on the programmer
and the PIC pins on the breadboard.
All tests were run at a target chip Vdd of 5V, which was verified to be
within spec. The controller chip always runs at 5V Vdd.
PGC and PGD are driven from digital outputs of the controller PIC to the
target chip via 2Kohm resistors. This is to deal with varying Vdd issues,
and to prevent damage when both PICs try to drive the line at the same time.
This can happen happen in an attempt to figure out the target PIC type. For
readback, the target chip PGD is connected thru another 2Kohm resistor to
the comparator input of the controller PIC.
I tried a number of things, none of which changed the symptoms at all:
1 - Added 10 cycles of NOP to the controller firmware before and after
clock edges. The controller is a 16F648A running at 20MHz, so this added an
additional 2uS between edges to what was already working with the ZIF
socket.
2 - Added 100mS of additional delay after any changes to Vpp and Vdd.
3 - Added 100nF of bypass capacitance right at the PIC on the breadboard.
This did reduce noise at the breadboard on Vdd slightly, but had no other
noticeable effect.
4 - Some additional pins other than the programming signals were driven in
the ZIF socket due to supporting different PIC pinouts. None of these were
supposed to matter according to the documentation. I hooked up all the pins
on the bread board the same way (additional connections to PGC, PGD, GND,
etc) but same symptom. Verified on scope that all pins were in fact driven
the same as when in the ZIF socket.
5 - Tied all remaining unused pins to ground via 10Kohm resistors.
6 - Wrote separate host program that used only the lowest level commands
to explicitly set Vdd, Vpp, PGC, and PGD directly from the host. There was
now at least one RS-232 command byte and a response byte between any two
transitions on any of the lines, in addition to specific longer timeouts to
make sure Vpp and Vdd stabalized. Verified all this on scope. At this slow
rate, signals now looked perfectly square on scope (couldn't seen edges at
all, only high and low levels). Could clearly see time between clock and
data edges on scope at 1mS/division setting.
7 - Added 650ohm pulldown on Vpp and 420ohms pulldown on Vdd. This made
the fall times sharper. The programmer regulates these voltages and this is
within its drive capabilities. Verified that both voltages were still
regulated to well within spec of 13V and 5V when enabled.
Then I tried something that DID make it work on the breadboard with the same
software and firmware while still working in the ZIF socket. This also
proved that everything was wired correctly and no parts were broken. Can
you guess what it was?
Now I've got something that works, but I'm still trying to characterize it a
bit more and hopefully come up with a modification to the programmer to take
this into account. I'll give you a chance to think about the answer while I
figure out what the production solution will be. I'll post the explanation
and my final solution here in a day or two.
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2004\02\08@190635
by
Ken Pergola
|
Hi Olin,
Hey it's nice to see you ask for something. :)
Challenges are fun.
I hope it is not as esoteric as the skin effect differences of stranded
versus solid wire on the cable going to your target. :)
Seriously, I'll take a stab:
1) How about pull down resistors on the PGC and PGD lines at the programmer
end of things (not at the target side)?
2) You never mentioned what you Vpp rise time is.
I'm assuming you don't have any capacitor hanging from /MCLR to ground
since you did not mention that in your post, correct?
3) Your target PIC on the breadboard does not have Fosc supplied to it
correct?
From your post I can infer that you don't have it on the breadboard, but
if you do, you might need to kill Fosc if your Vpp rise time does not meet
the programming specification of the current PIC.
4) Signal line ringing issues due to improper line termination? Perhaps 270
ohm series resistors instead of 2000 ohm resistors?
5) I hope you did not find out that the other target PIC pins not used
during ICSP are not floating while in programming mode? I hope this is not
true since the programming specs usually say that they do float.
6) Radix was not explicitly defined for every constant in your source code.
:)
(I could not resist Olin -- this is actually making fun of myself!)
I had to make an attempt to make you smile after all that frustrating
troubleshooting!
Hope things work out for you.
Take care Olin,
Regards,
Ken Pergola
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2004\02\08@192053
by
Ken Pergola
Or going to the other extreme:
You had two ICSP cables -- one was wired straight-through and the other was
wired crossed?
Best regards,
Ken Pergola
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2004\02\08@202251
by
Ian McLean
2004\02\08@202537
by
Olin Lathrop
Ken Pergola wrote:
> Hey it's nice to see you ask for something. :)
As I said, I've already solved the problem. I posted it because I thought
some here might find it interesting. It had me stumped for a whole day.
> 1) How about pull down resistors on the PGC and PGD lines at the
> programmer end of things (not at the target side)?
No need, since these are totem pole outputs of a 16F648A and are actively
driven both ways. The edges look nice and fast on a scope too.
> 2) You never mentioned what you Vpp rise time is.
> I'm assuming you don't have any capacitor hanging from /MCLR to
> ground since you did not mention that in your post, correct?
Right, just straight into the MCLR/Vpp pin. Vpp rise time wasn't the
problem.
> 3) Your target PIC on the breadboard does not have Fosc supplied to it
> correct?
The symptoms were observed with just the bare PIC connected to the 5
programming signals, GND, Vdd, Vpp, PGC, and PGD, via the 20 inch connection
I mentioned.
> From your post I can infer that you don't have it on the
> breadboard, but if you do, you might need to kill Fosc if your Vpp
> rise time does not meet the programming specification of the current
> PIC.
I was mostly testing with 18F PICs like the 18F1320. These use Vdd before
Vpp sequence. It's perfectly normal for these PICs to have power on for a
while before Vpp is raised to 13V.
> 4) Signal line ringing issues due to improper line termination?
> Perhaps 270 ohm series resistors instead of 2000 ohm resistors?
I don't want to go much below 2Kohm for other reasons, but you're getting
close.
> 5) I hope you did not find out that the other target PIC pins not used
> during ICSP are not floating while in programming mode? I hope this
> is not true since the programming specs usually say that they do
> float.
The programming spec seems to be correct in this regard.
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2004\02\08@202742
by
Olin Lathrop
Ken Pergola wrote:
> You had two ICSP cables -- one was wired straight-through and the
> other was wired crossed?
Everything was wired correctly and as described.
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2004\02\08@203020
by
Olin Lathrop
Ian McLean wrote:
> Maybe you needed pull-ups on the PGD and PGC lines - on the target
> side?
These are driven with nice clean digital signals at the other end of 2Kohm
resistors. Any appreciable pullup or pulldown would prevent the signal from
going all the way to either rail due to the voltage divider between the
pullup and the series 2Kohm.
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2004\02\08@204926
by
Ken Pergola
|
|
Hi Olin,
Ok, you're cliff-hanging me here -- this is worse than waiting for the
answer to the daily Jumble (TM):
> As I said, I've already solved the problem. I posted it because I thought
> some here might find it interesting. It had me stumped for a whole day.
I know -- I read you message several times, but I won't lose respect for you
if you ask for help from time to time. Everybody needs help at some time or
another. It is not a sign of weakness to ask for help.
> > 4) Signal line ringing issues due to improper line termination?
> > Perhaps 270 ohm series resistors instead of 2000 ohm resistors?
>
> I don't want to go much below 2Kohm for other reasons, but you're getting
> close.
No characteristic impedance problems?
Ground bounce? Adding some resistance (~25 ohms) in the ground lead between
your programmer and the target?
At least give me a few hints... :)
Best regards,
Ken Pergola
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2004\02\08@205927
by
Tony Nixon
2004\02\08@214329
by
Ken Pergola
Hi Olin,
> As a quick test I connected the RJ-12 to a few boards that had
> PICs on them and that worked with an ICD-2.
Hi Olin,
As you probably know, the ICD 2 has 4.7 K ohm pull-down resistors on PGC and
PGC.
Is it related to this? You mentioned that the breadboard target test worked
with the ICD 2 correct?
Regards,
Ken Pergola
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2004\02\08@230714
by
Anand Dhuru
Olin, I have been experiencing the exact same problem, as I wrote in the
other thread about 'Using The DIYK128 In An ICSP App'.
Of course, your description of the problem is far more precise and lucid.
The suggested cure from Bob and Outer was to add ample decoupling at the
breadboard end of the cable. This improved the operation quite a bit, but
its still nowhere failsafe.
I also noticed that the failures were more consistent with 8 pin devices as
against the larger PICs.
So, I am very very curious to know what finally solved the problem.
Regards,
Anand Dhuru
{Original Message removed}
2004\02\09@011739
by
Brent Brown
> > 4) Signal line ringing issues due to improper line termination?
> > Perhaps 270 ohm series resistors instead of 2000 ohm resistors?
>
> I don't want to go much below 2Kohm for other reasons, but you're
> getting close.
Wild guess(s). You shifted the 2k series resistors to the other end of the
cable and it started working? That way you get full drive to overcome cable
capacitance but retain the current limit ability you desire.
Or maybe a 1k at each end of the cable. Same reason as above.
But from what you have said about observed signal shape on the scope I
doubt I'm on the right track.
Brent.
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2004\02\09@012154
by
Anand Dhuru
|
|
Was the solution something as simple as using 5 wires rather than a 5 core
cable?
Anand
----- Original Message -----
From: "Brent Brown" <EraseMEbrent.brownspam_OUTTakeThisOuTCLEAR.NET.NZ>
To: <PICLISTspam_OUTMITVMA.MIT.EDU>
Sent: Monday, February 09, 2004 11:41 AM
Subject: Re: [PIC]: PIC programmer puzzle
> > > 4) Signal line ringing issues due to improper line termination?
> > > Perhaps 270 ohm series resistors instead of 2000 ohm resistors?
> >
> > I don't want to go much below 2Kohm for other reasons, but you're
> > getting close.
>
> Wild guess(s). You shifted the 2k series resistors to the other end of the
> cable and it started working? That way you get full drive to overcome
cable
{Quote hidden}> capacitance but retain the current limit ability you desire.
>
> Or maybe a 1k at each end of the cable. Same reason as above.
>
> But from what you have said about observed signal shape on the scope I
> doubt I'm on the right track.
>
> Brent.
>
>
>
> --
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2004\02\09@030553
by
SM Ling
> Then I tried something that DID make it work on the breadboard with the
same
> software and firmware while still working in the ZIF socket. This also
> proved that everything was wired correctly and no parts were broken. Can
> you guess what it was?
uF Capacitor to VCC or VDD line ?
Cheers, Ling SM
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2004\02\09@030555
by
Wouter van Ooijen
> > 4) Signal line ringing issues due to improper line termination?
> > Perhaps 270 ohm series resistors instead of 2000 ohm resistors?
>
> I don't want to go much below 2Kohm for other reasons, but
> you're getting
> close.
I recall that earlier versions of Wisp628 used 470 ohm series sesistors,
I now use 47 ohm.
But Olin, did you realy say you are using the programmer-PIC and the
programmed-PIC at different Vcc's with only a series resistor to prevent
touble? Naughty naughty you!
Wouter van Ooijen
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2004\02\09@030556
by
Wouter van Ooijen
Or maybe what I did (more than once!): I had both a PIC in the ZIP
socket *and* one connected to the ICSP leads. But I think that would not
take a few days to correct.
Wouter van Ooijen
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2004\02\09@041803
by
Wouter van Ooijen
> For
> readback, the target chip PGD is connected thru another 2Kohm
> resistor to
> the comparator input of the controller PIC.
Which value do you put on the other input of the comparator? I hope you
do switch the programmer-PIC output that drives the PGD line to input?
Wouter van Ooijen
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2004\02\09@072948
by
Olin Lathrop
Tony Nixon wrote:
> LVP pin floating???
Same symptom whether the PGM pin is left floating to tied to ground thru a
10Kohm resistor.
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2004\02\09@073155
by
Olin Lathrop
Ken Pergola wrote:
> As you probably know, the ICD 2 has 4.7 K ohm pull-down resistors on
> PGC and PGC.
These are driven actively in both directions by the controller PIC thru
2Kohm resistors.
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2004\02\09@073611
by
Olin Lathrop
Anand Dhuru wrote:
> The suggested cure from Bob and Outer was to add ample
> decoupling at the breadboard end of the cable. This improved the
> operation quite a bit, but its still nowhere failsafe.
One of the things I tried was to add 100nF decoupling capacitance right at
the target PIC. It did make Vdd a little cleaner as observed on a scope,
but had no effect on the symptom.
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2004\02\09@075102
by
Olin Lathrop
2004\02\09@075517
by
Olin Lathrop
SM Ling wrote:
> uF Capacitor to VCC or VDD line ?
I had tried a 100nF bypass cap at the target chip. This reduced noise on
Vdd, but had no effect on the symptom. You can't put a large cap on Vdd
because it needs to be switched. You would either have to add a large
timeout whenever Vdd was changed (which I did anyway as a test) or measure
it, which my circuit can't do.
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2004\02\09@075932
by
Olin Lathrop
Wouter van Ooijen wrote:
> But Olin, did you realy say you are using the programmer-PIC and the
> programmed-PIC at different Vcc's with only a series resistor to
> prevent touble? Naughty naughty you!
Well, um, yeah. Note that PGC and PGD are always held low unless Vdd is up
and stable. This means there is no chance of parasitic SCR latchup. But
yes, there will be some current thru the protection diode of the target chip
when being run at a low Vdd level.
However, all the tests I reported yesterday were with the target Vdd level
set to 5V, so this was not an issue in that case.
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2004\02\09@080139
by
Olin Lathrop
Wouter van Ooijen wrote:
> Or maybe what I did (more than once!): I had both a PIC in the ZIP
> socket *and* one connected to the ICSP leads. But I think that would
> not take a few days to correct.
I was mainly using one PIC for testing, so I haven't (yet) done that. That
wasn't the problem.
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2004\02\09@080801
by
Wouter van Ooijen
> Well, um, yeah. Note that PGC and PGD are always held low
> unless Vdd is up
> and stable. This means there is no chance of parasitic SCR
> latchup. But
> yes, there will be some current thru the protection diode of
> the target chip
> when being run at a low Vdd level.
Note that there will also be protection diode current through your
progger-PIC when you run the target at 6.0 Volt (max for a 16C84), or
are you running the progger PIC at 5.5 and limiting the Vhigh to 5.5?
This different-Vcc issue is one of the things that kept me from
designing a production-grade version of Wisp628.
In the older WISP I solved this by running the progger-PIC at the same
voltage as the target. In those days the 16C84 was the only target, and
the progger-PIC was of course a 16C84. This approach did have some funny
interaction with Vcc-dependent Vpp generator :(
Wouter van Ooijen
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2004\02\09@080802
by
hael Rigby-Jones
|
>>Ken Pergola wrote:
>> 4) Signal line ringing issues due to improper line termination?
>> Perhaps 270 ohm series resistors instead of 2000 ohm resistors?
>From: Olin Lathrop [KILLspamolin_piclistspamBeGoneEMBEDINC.COM]
>I don't want to go much below 2Kohm for other reasons, but
>you're getting close.
Crosstalk between PGC and PGD? Those breadboards have a lot of capacitance
between adjacent rows.
Regards
Mike
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2004\02\09@080803
by
Olin Lathrop
Wouter van Ooijen wrote:
>> For
>> readback, the target chip PGD is connected thru another 2Kohm
>> resistor to
>> the comparator input of the controller PIC.
>
> Which value do you put on the other input of the comparator? I hope
> you do switch the programmer-PIC output that drives the PGD line to
> input?
The other comparator input is derived from 1/2 the Vdd level with a little
filtering. This allows the threshold to adjust as the Vdd level is
adjusted.
I don't remember whether I let the PGD driver float or not. That is another
reason for the 2Kohm resistor. Both the controller and target chip can be
driving PGD at the same time with no ill effects. The target chip drivers
can easily overcome 2Kohms to ground. That's only 2.8mA with Vdd at the
maximum of 5.5V.
In any case, the PGD readback signal at the target chip looks nice and
clean.
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2004\02\09@081802
by
Olin Lathrop
Wouter van Ooijen wrote:
> Note that there will also be protection diode current through your
> progger-PIC when you run the target at 6.0 Volt (max for a 16C84), or
> are you running the progger PIC at 5.5 and limiting the Vhigh to 5.5?
The circuit can adjust Vdd up to 6V, but so far I've only used it at 5.5V.
Again however, the target Vdd will be brought up long after the controller
is powered up, so there is no danger of SCR latchup. Even if you figure
only 500mV drop accross the protection diode and a Vdd of 6V, that's only
250uA thru the diode. The other direction is the worse case. With a target
Vdd of 2V there will be 1.25mA thru the protection diodes of the target PIC.
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2004\02\09@112827
by
Intosh, Ph.D.
|
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
source= http://www.piclist.com/piclist/2004/02/08/175826a.txt?
Olin Lathrop says:
>6 - Wrote separate host program that used only the lowest level commands
>to explicitly set Vdd, Vpp, PGC, and PGD directly from the host. There
>was now at least one RS-232 command byte and a response byte between any
>two transitions on any of the lines, in addition to specific longer
>timeouts to make sure Vpp and Vdd stabalized. Verified all this on
>scope. At this slow rate, signals now looked perfectly square on scope
>(couldn't seen edges at all, only high and low levels). Could clearly see
>time between clock and data edges on scope at 1mS/division setting.
The "customer complaint" is in "read" and you have detailed an exhaustive
"write" debug scenario.
Following your step 6, I would display the device ID as it was read back.
(verify original complaint) This should have been done initially, but it
is a somewaht subtle point.
Assuming failure, I would do the setup for the read device ID, then set up
a program where I could toggle the clock line high or low, and read the
return voltage as I clock out the ID from the target device.
As a design question, why not do a turn-around on the data pin on the
programmer, instead of having a voltage divider and a more complex circuit?
- ---
Aubrey McIntosh
http://www.piclist.com/member/AM-vima-Y84
PIC/PICList FAQ: http://www.piclist.com
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2004\02\09@132252
by
Wouter van Ooijen
> As a design question, why not do a turn-around on the data pin on the
> programmer, instead of having a voltage divider and a more
> complex circuit?
That would not work well if the programmer PIC runs at 5V and the target
at 3 Volt.
Wouter van Ooijen
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2004\02\09@134611
by
Mike Hawkshaw
|
|
Olin,
Others have hinted at transmission line effects, which was my first thought
when I read your post, but from your responses this seems not to be the
case.
The only line you don't say much about is the Vpp line, so I'm thinking the
problem might be there.
I wonder if you have a series resistor in the line driving the Vpp pin?
There is an issue with this line and spikes on the 18 series PICs but I
don't know if this also applies when in programming mode.
Another thing I would have looked at would have been the rise times of the
Vdd and Vpp supplies. In 7 you said that you had looked at fall times, so
maybe that was what you looked at next.
Whatever it was, I'm wondering if (as 20" of cable is not much) it was only
just working in the ZIF socket, and the extra cable was the straw that broke
the cammels back?
Best regards...Mike.
----- Original Message -----
From: "Olin Lathrop" <.....olin_piclistRemoveMEEMBEDINC.COM>
To: <RemoveMEPICLISTspamBeGoneMITVMA.MIT.EDU>
Sent: Sunday, February 08, 2004 10:57 PM
Subject: [PIC]: PIC programmer puzzle
> Here is a purely academic puzzle, as I've already found a solution.
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2004\02\09@145304
by
Ken Pergola
|
|
Mike Hackshaw wrote:
> ...I wonder if you have a series resistor in the line driving the Vpp pin?
>
> ...Another thing I would have looked at would have been the rise times of
the
> Vdd and Vpp supplies...
Hi Mike,
The only catch is the 'size' of this resistance: you want to keep the Vpp
source impedance (and the impedance of its switching circuitry) as low as
possible if you want to conform to any of the Microchip programming
specifications that dictate a Vpp rise time of < 1 uS.
It does not take much Vpp source impedance coupled with any external
capacitance a user may have on the target PIC's Vpp pin to violate this part
of the specification.
The Microchip ICD 2 uses a Vishay/Siliconix DG411DY quad SPST CMOS analog
switch for Vpp switching. I would venture to guess that they are paralleling
a few of the switches to lower the Rds ON of the 'composite' Vpp switch to
help in this regard.
Best regards,
Ken Pergola
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2004\02\09@161650
by
John N. Power
|
|
> From: Olin Lathrop[SMTP:olin_piclistEraseMEEMBEDINC.COM]
> Sent: Sunday, February 08, 2004 8:24 PM
> To: RemoveMEPICLISTEraseMEspam_OUTMITVMA.MIT.EDU
> Subject: Re: [PIC]: PIC programmer puzzle
>> 4) Signal line ringing issues due to improper line termination?
>> Perhaps 270 ohm series resistors instead of 2000 ohm resistors?
> I don't want to go much below 2Kohm for other reasons, but you're getting
> close.
Line termination must be done at both ends of the line. Your line has 2k
resistors at the source end (the controller PIC); it also needs termination
at the load end. Voltage overshoot can occur at the open end of the line.
Putting the target PIC in the ZIF socket exposes it only to the input of the
line. Put it at the other (open or misterminated) end exposes it to transients
which are not seen at the source. You have resistors to ground on the Vdd
and Vpp lines, but you said nothing about the clock and data lines.
Capacitors to ground from the end of the 2k resistors would calm things
down. Terminating resistors at the breadboard end would be better if the
controller could drive them (but not with series 2k resistors).
John Power
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2004\02\09@164319
by
Wouter van Ooijen
> Line termination must be done at both ends of the line.
I would be surprised if that was the problem. In my programmer I have
resistors (47 ohm) at the programmer side only. I have used cables up to
2 meter without any problem.
Wouter van Ooijen
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2004\02\09@220532
by
Ken Pergola
|
|
Olin Lathrop wrote:
> ...Then I tried something that DID make it work...
> ...Can you guess what it was?...
1) You tried a trapezoidal line driver and line driver/receiver on the
SCLK/SDATA lines (respectively)?
Like we say with the weather, "It's not the heat it's the humidity."
In electronics: "It's not the frequency, it's the edge transitions."
Hmm, I do not see any *explicit* rise/fall time restrictions on SCLK/SDATA
in the programming specification I'm looking at right now, but I do see a
capacitive loading specification on SDATA of 50 pF max of capacitance.
Probing questions:
1) Did you find significant ringing on Vpp that caused Vpp to dip below
the VIHH spec on the down swing of the ringing -- thus causing programming
mode to inadvertently exit?
2) Is the problem related to the target chip's package parasitic
inductance?
I'm enjoying this challenge, we should do more of these on the PICLIST.
I think you are going to hit us all with something good on April 1st. I will
be ready. :)
Best regards,
Ken Pergola
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2004\02\10@111114
by
Anand Dhuru
Is this thread concluded?
I didn't see a solution to the puzzle, what finally cured the problem; would
love to know that.
Regards,
Anand
{Original Message removed}
2004\02\11@162229
by
John N. Power
> From: Wouter van Ooijen[SMTP:spamBeGonewouterEraseMEVOTI.NL]
> Sent: Monday, February 09, 2004 4:40 PM
> To: PICLISTspamBeGoneMITVMA.MIT.EDU
> Subject: Re: [PIC]: PIC programmer puzzle
>> Line termination must be done at both ends of the line.
> I would be surprised if that was the problem. In my programmer I have
> resistors (47 ohm) at the programmer side only. I have used cables up to
> 2 meter without any problem.
> Wouter van Ooijen
47 ohms may be closer to the characteristic impedance of the line. Absorption
of the reflected voltage is optimal only if the terminating resistor has resistance
equal to that of the line. Perhaps 2k is too large to do this.
John Power
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