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'[PIC]: PIC on FPGA?'
2001\05\02@132847
by
Saurabh Sinha
2001\05\02@154214
by
Andrew Warren
2001\05\02@220216
by
Jay.R.Vijay-Indra
At 19:20 02/05/01 -0700, you wrote:
>Hi,
>
>Anyone tried something like trying to implement a PIC on an FPGA?
>
Yes this has been done about 4 or 5 years back. Very nice chap called
Thomas.A.Coonan posted a file called SYNTHPIC.ZIP on his web site. This
file had a VHDL core for PIC CPU and couple of other VHDL files for I/O
ports and some test files.
I implemented them with some modifications on Xilinx 4005 and manage to get
40Mhz clock speed. It was fun.
Check http://www.mindspring.com/~coonan, I am sure file is still there. If not I
will try and find it on my old hard disk.
Regards,
Jay
>
>
>
>
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2001\05\02@223718
by
Bob Ammerman
I looked closely at this a few months back.
It was an impressive piece of work.
I did find a couple of small bugs in the VHDL. I corresponded with Mr.
Coonan and he was going to fix them. I don't know if the updated code has
been posted.
Bob Ammerman
RAm Systems
(contract development of high performance, high function, low-level
software)
{Original Message removed}
2001\05\02@232251
by
Bob Ammerman
I went on a hunt...
Here is the corrected URL:
http://www.bomis.com/rings/Mhardware-open_source-computers/20
The bug fixes listed include the ones I found:
- Generalized PC write so that you can do fancy computed-goto types of
things
- Fixed STATUS register update. For example, Clearing STATUS actually now
causes Z to be set
Bob Ammerman
RAm Systems
(contract development of high performance, high function, low-level
software)
{Original Message removed}
2001\05\03@023951
by
David Cary
2001\05\03@133753
by
Saurabh Sinha
2001\05\03@135421
by
Jay.R.Vijay-Indra
At 19:20 02/05/01 -0700, you wrote:
>Hi,
>
>Anyone tried something like trying to implement a PIC on an FPGA?
>
Yes this has been done about 4 or 5 years back. Very nice chap called
Thomas.A.Coonan posted a file called SYNTHPIC.ZIP on his web site. This
file had a VHDL core for PIC CPU and couple of other VHDL files for I/O
ports and some test files.
I implemented them with some modifications on Xilinx 4005 and manage to get
40Mhz clock speed. It was fun.
Check http://www.mindspring.com/~coonan, I am sure file is still there. If not I
will try and find it on my old hard disk.
Regards,
Jay
>
>
>
>
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2001\05\03@140918
by
jamesnewton
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