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'[PIC]: Migrating to PIC16F84 - What am I doing wro'
2002\01\01@225558 by Sean Alcorn - Avion Sydney

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Hi there,

I am fairly new to the PIC, however I have now designed 3 successful
applications using the PIC12C508A

I have now designed a far more complex application which will probably end
up in a PIC16C505 - however I am developing it on a PIC16F84 to get it
going.

I burnt my first version in a PIC16F84 (NOT A version) this morning and
NOTHING. I checked all my hardware and retried - still nothing. I then
stripped everything out of the application so that it was just an LED
flashing at 1Hz.

I am running a 4.0 MHz crystal with 22pF caps. I have simply an LED
connected to RB7, Pin4 (MCLR) and all unused inputs tied high.

Can anybody see what I have done wrong? What have I missed?

Regards,

Sean


    LIST P= 16F84
    INCLUDE "P16F84.INC"
    RADIX DEC
    ORG  0X5
AUX1_L EQU  0XC
AUX1_H EQU  0XD
AUX2_L EQU  0XE
AUX2_H EQU  0XF
AUX EQU  0X10
S0 EQU  0X11
    __CONFIG   _CP_OFF &  _PWRTE_OFF & _WDT_OFF & _XT_OSC
    MOVLW  B'1111'
    MOVWF  TRISA
    MOVLW  B'00000000'
    MOVWF  TRISB
STARTHERE
    MOVLW  B'00000000'
    MOVWF  PORTB
    PAGESEL (DELAY500)
    CALL   DELAY500
    MOVLW  B'10000000'
    MOVWF  PORTB
    PAGESEL (DELAY500)
    CALL   DELAY500
    PAGESEL (STARTHERE)
    GOTO   STARTHERE
DELAY500
    ; CREATE A DELAY OF 500MS
    MOVLW  9;*
    MOVWF  AUX2_L
DELAYLAB32
    MOVLW  169;*
    MOVWF  AUX1_H;*
DELAYLAB22
    MOVLW  81;*
    MOVWF  AUX1_L;*
DELAYLAB12
    CLRWDT
    DECFSZ AUX1_L, F;*
    PAGESEL (DELAYLAB12)
    GOTO   DELAYLAB12
    CLRWDT
    DECFSZ AUX1_H, F;*
    PAGESEL (DELAYLAB22)
    GOTO   DELAYLAB22
    CLRWDT
    DECFSZ AUX2_L, F;*
    PAGESEL (DELAYLAB32)
    GOTO   DELAYLAB32
    RETURN
    END

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2002\01\01@230612 by jim

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Isn't MCLR an input pin only?

                   Regards,

                       Jim
----- Original Message -----
From: Sean Alcorn - Avion Sydney <.....sdalcornKILLspamspam@spam@AVION.COM.AU>
To: <PICLISTspamKILLspamMITVMA.MIT.EDU>
Sent: Tuesday, January 01, 2002 8:52 PM
Subject: [PIC]: Migrating to PIC16F84 - What am I doing wrong?


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2002\01\01@231020 by Thet Naing Kyaw

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Hi,
   I think the code should be something like the
following.
  LIST P= 16F84
  INCLUDE "P16F84.INC"
  RADIX DEC
  AUX1_L EQU  0X0C
  AUX1_H EQU  0X0D
  AUX2_L EQU  0X0E
  AUX2_H EQU  0X0F
  AUX EQU  0X10
  S0 EQU  0X11
  __CONFIG   _CP_OFF &  _PWRTE_OFF & _WDT_OFF
&_XT_OSC

    ORG  0x00
    GOTO BEGIN
    ORG  0X05
BEGIN
     MOVLW  B'1111'
     MOVWF  TRISA
     MOVLW  B'00000000'
     MOVWF  TRISB
STARTHERE
     MOVLW  B'00000000'
     MOVWF  PORTB
     PAGESEL (DELAY500)
     .
     .
     .
     END

Rgds,
Thet Naing Kyaw

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wrote:
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2002\01\01@231433 by Jinx

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I think it's your start vector

start equ 0x00

goto start

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2002\01\01@232750 by Sean Alcorn - Avion Sydney

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on 3/7/07 4:04 PM, jim at spamBeGonejamespspamBeGonespamINTERTEX.NET wrote:

> Isn't MCLR an input pin only?

Yes it is.

Sean

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2002\01\01@233659 by jim

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Never mind.  I read it wrong.

                       Regards,

                           Jim

----- Original Message -----
From: Sean Alcorn - Avion Sydney <RemoveMEsdalcornspamTakeThisOuTAVION.COM.AU>
To: <PICLISTEraseMEspam.....MITVMA.MIT.EDU>
Sent: Tuesday, January 01, 2002 9:26 PM
Subject: Re: [PIC]: Migrating to PIC16F84 - What am I doing wrong?


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2002\01\02@001157 by parkiss

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Sean-

Maybe your assembler detects and automagically sorts this out for
you, but if not:

{Quote hidden}

The PAGESEL directives are generating instructions, which are skipped
on zero rather than your subsequent GOTO instructions. Result--the
GOTO is always executed and you never return from the subroutine. Try
commenting out the PAGESEL directives to see if this is indeed the
problem.

Hope that helps,

Steve

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2002\01\02@003933 by Sean Alcorn - Avion Sydney

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on 1/1/02 11:59 PM, S Parkis at RemoveMEparkissTakeThisOuTspamspamEARTHLINK.NET wrote:

Hi Steve,

Thanks for your reply.

> The PAGESEL directives are generating instructions, which are skipped
> on zero rather than your subsequent GOTO instructions. Result--the
> GOTO is always executed and you never return from the subroutine. Try
> commenting out the PAGESEL directives to see if this is indeed the
> problem.

My silly BASIC to Assembler compiler puts these in. When I build the file
with MPLAB, I get a "message" that the PAGESEL is not necessary, and no code
was generated. But I will comment them out and try again.

On a related note though, I also get another two messages - relating to
lines 13 and 15 - (MOVWF TRISA and MOVWF TRISB) - "Register in operand not
in bank 0. Ensure that bank bits are correct." - so I now suspect this could
be my problem. I do not understand this bank switching stuff.

Cheers,

Sean

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2002\01\02@005214 by Jinx

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> lines 13 and 15 - (MOVWF TRISA and MOVWF TRISB) - "Register
> in operand not in bank 0. Ensure that bank bits are correct." - so I
> now suspect this could be my problem. I do not understand this bank
> switching stuff

Those are just warning messages. You are being advised to check
that the correct register is being worked on. You'll find in the include
file (trisa equ 0x85 and trisb equ 0x86) that you are, and no specific
bank switching is required on the F84. If you migrate to the F628,
then you will have to use rp0 and rp1 to access the tris registers

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2002\01\02@112608 by Roman Black

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Sean Alcorn - Avion Sydney wrote:
{Quote hidden}

Your code does not have the register
setups? Check how you set up the OPTION
etc. :o)
-Roman

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2002\01\02@120543 by Fabio Pereira

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Hi Sean:

The banking capability is an issue to allow PICs to have more than 128
registers (while using the same 12 or 14 bit instruction length).
As a Standard (and for compatibility), the TRIS registers are located in
bank 1 ,while the PORT registers are found in bank 0 (for the f84).
The registers maps for the midrange family may be found at DS31006A pages
6-10 and 6-11. There you will be able to make a comparison between the F84
memory map (as fig 6-6, page 6-11) and the more advanced devices (like F628,
876,877).
Se same physical address is used to access both the PORT and TRIS registers,
the only diference is the bank selection bits RP0 and RP1 found in the
STATUS reg.
These warnings are indications that you need to use bank switching
instructions to ensure you are working with the correct register.
Note that even using an instruction like BSF STATUS,RP0 will make the MPASM
still believe in bank 0 (while it compiles and generates the correct code
...)
By using the BANKSEL macros you will ensure to work always in the correct
bank and will take those warnings off too.

that's it, I wish it helps...

Fabio Pereira

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2002\01\02@120551 by Fabio Pereira

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> Those are just warning messages. You are being advised to check
> that the correct register is being worked on. You'll find in the include
> file (trisa equ 0x85 and trisb equ 0x86) that you are, and no specific
> bank switching is required on the F84. If you migrate to the F628,
> then you will have to use rp0 and rp1 to access the tris registers
>
Jinx:

I think the F84 really needs the RP0 bit as it has two memory banks ...

Fabio Pereira

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2002\01\02@131226 by Fabio Pereira

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Sean:

Your start address (0x5) is not correct. If you want to use it you should
do:
ORG 0x0
GOTO START
ORG 0x5
START
....
>      MOVLW  B'1111'
>      MOVWF  TRISA
>      MOVLW  B'00000000'
>      MOVWF  TRISB
> STARTHERE
>      MOVLW  B'00000000'
>      MOVWF  PORTB
>      PAGESEL (DELAY500)

The PAGESEL is not needed in 1k devices (as F84A)...

{Quote hidden}

You do not need to clear the watchdog timer since you disabled it (WDT_OFF
directive), it works only to spend one instruction cycle ... (somethin like
a NOP would do the same, without affecting the TO and PD flags.)

{Quote hidden}

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2002\01\02@153844 by Jinx

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> Jinx:
>
> I think the F84 really needs the RP0 bit as it has two memory banks ...

Yes, but you don't need to use it for accessing the tris registers.
These lines are clipped from a program I use quite regularly for
the F84 (it was written a long time ago in a different environment,
and MPLAB still squawks about using trisa)

porta  equ 05h        ;port a address
portb  equ 06h        ;     b
trisa  equ 85h        ;     a direction
trisb  equ 86h        ;     b

start  equ 00h        ;program start vector

   org start         ;define program start vector
   goto entry

entry    movlw  10h
           tris   porta     ;porta ...i oooo
           movlw  00h
           tris   portb     ;portb oooo oooo
           movlw  80h
           option
          ..............

=================

And how the banksel bits must be used in the F628 in a very
similar program

start  equ 0x00       ;program start vector

        org 0x00
        goto entry

entry    clrf   porta
           movlw  0x07    ;comparators off
           movwf  cmcon
           clrf   status       ;bank0 (clear rp0 and rp1)

(snip)

        bsf    status,rp0    ;select bank1
        bcf    status,rp1

        movlw  0x00        ;oooo oooo
        movwf  trisa
        movlw  0x02        ;oooo ooio
        movwf  trisb

        movlw  0x80                ;portb pull-ups off
        movwf  option_reg

        bcf    status,rp0    ;back to bank0
        bcf    status,rp1

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2002\01\02@170204 by Fabio Pereira

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{Quote hidden}

I agree, but you are talking about the tris instruction: it's  use is not
recommended by Microchip (well, only for future compatibility ...) :-D

At least, the EECON1 and EECON2 will need the RP0=1 to be accessed
(OPTION_REG too, but there is an option instruction too ...) :-D

But that's ok I'm just trying to help .. hehe

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2002\01\02@173207 by Jinx

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>
> But that's ok I'm just trying to help .. hehe

It was worth pointing out for Steve's benefit. A lot of micros
don't have the bank-switching issues that PICs do

How about this for another T-shirt Mr Newton

  PICking
       is
    RISCy
  business

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