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PICList Thread
'[PIC]: Interrupt determinism'
2000\08\21@201828 by Bob Ammerman

picon face
Stephen said:
"While PIC may be marketed as such, Scenix is the only truly
deterministic 8-bit architecture. Determinism not only applies to fixed
cycle length for a given instruction, but also a fixed interrupt response
time. While PIC may have the former, it's architecture has a variable
interrupt response, depending on what executing instruction was
interrupted."

I don't think this is strictly true. I am pretty certain some (all?) PICs
are fully deterministic on interrupt response for external interrupts. They
simply delay an interrupt that occurs during a single cycle instruction by
one extra cycle relative to one that occurs during a two cycle instruction.

For internal interrupts it doesn't happen that way, but you can sometimes
dejitter the interrupt by looking at, for example, the timer register. I do
this last on an 18C part to get a zero jitter interrupt based on timer 2.

Bob Ammerman
RAm Systems
(contract development of high performance, high function, low-level
software)

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2000\08\22@101505 by jamesnewton

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Errr... Bob, could you go into a bit more detail on that?

I seem to be completely missing how timer 2 would allow you to
"de-jitter-ize" the interrupt. Are you referring to timer based interrupts
only? If so, doesn't that restrict you to certain narrow setting of the
prescaler etc...?

Also, none of the PICs I've looked at provide that "equalizing" delay you
are referring to. Could you (or anyone) point to one?

Anyway, just in case anyone is not following why this is important: If the
ISR gets control in x cycles when the external interrupt occurred during a
single cycle instruction and in x+y cycles if the interrupt occurred while a
two cycle instruction was being executed, then I can't guaranty that my ISR
will respond to the external event without "jitter". i.e. being a bit late
one time and a bit early another in a random fashion.

---
James Newton .....jamesnewtonKILLspamspam@spam@geocities.com 1-619-652-0593


{Original Message removed}

2000\08\22@150609 by Olin Lathrop

flavicon
face
> I seem to be completely missing how timer 2 would allow you to
> "de-jitter-ize" the interrupt. Are you referring to timer based interrupts
> only? If so, doesn't that restrict you to certain narrow setting of the
> prescaler etc...?

I can't see how you could use timer 2 either, because there is no way to
know what the timer value was when the asynchonous external interrupt
occurred.  That would require use of a CCP module and timer 1.  Of course
this is different if the interrupt was generated by the timer in the first
place, but that's not what I thought this discussion was about.


By the way, James, did you know that when I do a normal REPLY to one of your
messages using MS Outlook Express it gets addressed to you and not the list?
Most other replies go to the list as expected.  That may explain why
sometimes my messages seem to get lost, because they go to a specific person
and not the whole list.  I thought the list server stomped on the REPLY-TO
address.  I just checked the header of your message, and the REPLY-TO
address was set to you.


*****************************************************************
Olin Lathrop, embedded systems consultant in Devens Massachusetts
(978) 772-3129, olinspamKILLspamcognivis.com, http://www.cognivis.com

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2000\08\22@154750 by jamesnewton

face picon face
Bob was (it turns out) talking about timer interrupts with regard to this
trick. He emailed me offlist (perhaps for the reason mention? <GRIN>) and
explained what he was doing with a snippet of code. Its actually a nice
little trick. I've asked his permission to post it on the piclist.com site
but haven't heard back yet.

Apparently only the newest PICs (18C's) support deterministic interrupts by
adding delays to interrupt handling based on the type of instruction that
was being executed when the interrupt occurred. Reaction to Scenix? <GRIN>

In my email client, I have a reply-to address set. The list server respects
that and carries it forward. You can override it when you reply if you wish.
I find it useful to reduce bandwidth when posting as an admin. We don't get
so many "Well, who died and made you king..." post to the list anymore do
we? <VBG> Just kidding.

---
James Newton (PICList Admin #3)
.....jamesnewtonKILLspamspam.....piclist.com 1-619-652-0593
PIC/PICList FAQ: http://www.piclist.com or .org

{Original Message removed}

2000\08\22@183546 by Bob Ammerman

picon face
Timer 2 has nothing to do with de-jitter-izing external ints. Only internal.
Sorry to disappoint.

I'm still pretty sure that the 18C provides dejitter for external ints
itself.

Here is a quote from section 7.0 of DS30062B near the end of page 65
(datasheet for 18C parts):

<QUOTE>
For external interrupt events, such as the INT pins or
the PORTB input change interrupt, the interrupt latency
will be three to four instruction cycles. The exact
latency is the same for one or two cycle instructions.
<END QUOTE>


Bob Ammerman
RAm Systems
(contract development of high performance, high function, low-level
software)

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http://www.piclist.com hint: PICList Posts must start with ONE topic:
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