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'[PIC]: I2C slave software for the PC to talk to a '
2001\05\17@114711 by kc0

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The I2C resources on the piclist.com site and in the archives and on google
don't seem to include PC I2C slave software...

...which would seem to be very useful for testing PIC I2C masters...

...am I just missing it?

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{Original Message removed}

2001\05\17@121210 by Michael Rigby-Jones

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Reason being it is very difficult to write a pure bit bashed slave on a PC
that will run at reasonable speeds.  You really need a small amount of
external logic to make this feasable, something to detect stop/start
conditions, and a shift register.  You can get I2C bus analysers for PC's
but they are *expensive*.  I have thought of using a PIC with an SSP based
slave and async comms to the PC, but I feel that introduces another layer of
potential problems, especialy with the slightly iffy SSP module...

Maybe we (as in list collective) can come up with a suitable design?

As an aside, if anyone is in the market for a good scope , the HP Infinium
series have I2C triggering built in, you can trigger on start/stop or a
specific byte.  Very usefull for debugging.

Cheers

Mike

> {Original Message removed}

2001\05\17@150613 by Olin Lathrop

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> The I2C resources on the piclist.com site and in the archives and on
google
> don't seem to include PC I2C slave software...
>
> ...which would seem to be very useful for testing PIC I2C masters...
>
> ...am I just missing it?

What hardware would you have the PC use for IIC?  "Standard" PCs don't come
with IIC ports.  IIC requires two open collector drivers.  I vaguely
remember that some of the parallel port control lines are open collector,
but am not sure.  Even if so, you would need to write a custom kernel mode
device driver to mess with the parallel port in a non-standard way.  It
would be easier to hook a PIC to a serial port or parallel port and have it
do IIC for the PC.

Besides, IIC is not well suited for distance like RS-232 is.  I think of IIC
as being an "on board" bus.


********************************************************************
Olin Lathrop, embedded systems consultant in Littleton Massachusetts
(978) 742-9014, .....olinKILLspamspam@spam@embedinc.com, http://www.embedinc.com

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2001\05\18@030329 by Michael Rigby-Jones

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{Quote hidden}

I2C master out of the parallel port is very simple, even through VB and on
NT based OS with freely available port drivers.  There is a linux I2C driver
available.

The "slave " part of the topic is the tricky bit...

Mike

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2001\05\18@031644 by Roman Black

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> > From: James Newton [SMTP:EraseMEjamesnewtonspam_OUTspamTakeThisOuTPICLIST.COM]
> > Sent: Thursday, May 17, 2001 4:40 PM
> > To:   PICLISTspamspam_OUTMITVMA.MIT.EDU
> > Subject:      [PIC]: I2C slave software for the PC to talk to a PIC
> >
> > The I2C resources on the piclist.com site and in the archives and on
> > google
> > don't seem to include PC I2C slave software...
> >
> > ...which would seem to be very useful for testing PIC I2C masters...
> >
> > ...am I just missing it?

Michael Rigby-Jones wrote:
> Reason being it is very difficult to write a pure bit bashed slave on a PC
> that will run at reasonable speeds.  You really need a small amount of
> external logic to make this feasable, something to detect stop/start
> conditions, and a shift register.


Olin Lathrop wrote:
> What hardware would you have the PC use for IIC?  "Standard" PCs don't come
> with IIC ports.  IIC requires two open collector drivers.  I vaguely
> remember that some of the parallel port control lines are open collector,
> but am not sure.  Even if so, you would need to write a custom kernel mode
> device driver to mess with the parallel port in a non-standard way.  It
> would be easier to hook a PIC to a serial port or parallel port and have it
> do IIC for the PC.


Yeah, it can be done fine. I'm always connecting PIC
stuff to my parallel port. I don't see the speed as
much of a problem, 100kbps should be fine, don't know
if you would get 400kbps but it might be possible.

I would use 3 pins of the PC par port, 2 as inputs for
the SDA and SCL, and one (output) through a diode which
would be used to pull the SDA low for acks etc. Probably
3 resistors and one diode needed.

I write stuff in Turbo C for dos, you can read and write
the port with ONE asm instruction and provided you can
go to dos mode and kill that windows POS you can get
some pretty impressive port performance. That's one
reason I stick with Win95, you can force dos mode.

The lead length is not that critical at 100kbps, probably
a few feet would be ok. :o)
-Roman

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2001\05\18@033738 by Michael Rigby-Jones

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{Quote hidden}

Roman,

You are talking about an I2C Master implementation which is pretty trivial
compared to a slave.  I'm starting to get interested in designing a cheap
bus analyser though.  Will have to do some "back of envelope engineering" at
lunch time!

Mike

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2001\05\18@043231 by Clive Frederickson

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Philips make an IIC to 8bit parallel interface chip PCD8584 (I think but may
be  different number) I have used this chip, it is easy to interface to and
supports full master mode. Perhaps connecting this to the parallel port ?

Regards

Clive Frederickson
R&D Technician (CECF Group)

       ----------
       From:  Michael Rigby-Jones [SMTP:TakeThisOuTmrjonesEraseMEspamspam_OUTNORTELNETWORKS.COM]
       Sent:  17 May 2001 17:01
       Subject:  Re: [PIC]: I2C slave software for the PC to talk to a PIC

       Reason being it is very difficult to write a pure bit bashed slave
on a PC
       that will run at reasonable speeds.  You really need a small amount
of
       external logic to make this feasable, something to detect stop/start
       conditions, and a shift register.  You can get I2C bus analysers for
PC's
       but they are *expensive*.  I have thought of using a PIC with an SSP
based
       slave and async comms to the PC, but I feel that introduces another
layer of
       potential problems, especialy with the slightly iffy SSP module...

       Maybe we (as in list collective) can come up with a suitable design?

       As an aside, if anyone is in the market for a good scope , the HP
Infinium
       series have I2C triggering built in, you can trigger on start/stop
or a
       specific byte.  Very usefull for debugging.

       Cheers

       Mike

       > {Original Message removed}

2001\05\18@044524 by Michael Rigby-Jones

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Just been looking at the datasheet of the PCF8584.  This supports full
Master/Slave and monitor mode, where it can be used to monitor bus
transaction between a slave and a master without interfereing.  ISTR that
Elektor electronics magazine had an project for interfacing one of these
chips to a parallel port.  I'll have to look back through my pile of mags
when I get home.

Not sure how much this device is, or it's availability.  Farnell don't seem
to list it in the latest catalogue which probably isn't a good sign.

Regards

Mike

> {Original Message removed}

2001\05\18@065658 by Bob Ammerman

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And at any decent bit rate you'll get clobbered by something as simple as
timer interrupts.

I do this sort of thing too, but I get rid of DOS and 'take over the box' to
do it.

Bob Ammerman
RAm Systems
(contract development of high performance, high function, low-level
software)

{Original Message removed}

2001\05\18@085241 by Roman Black

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Michael Rigby-Jones wrote:

{Quote hidden}

No i'm talking about a slave, which should not
be hard to do at all. Why do you see such a problem??
:o)
-Roman



> Mike
>
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2001\05\18@090120 by Roman Black

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Bob Ammerman wrote:
>
> And at any decent bit rate you'll get clobbered by something as simple as
> timer interrupts.
>
> I do this sort of thing too, but I get rid of DOS and 'take over the box' to
> do it.


This is sounding like a challenge? Am I the only
PC programmer that thinks this is a pretty easy task??

Bob, what do you see as the "decent" bit rate that
will start to stump the PC?? I too "take over the box"
in dos programs and do some timing critical stuff with
the parallel port, and this doesn't look that hard.
-Roman

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2001\05\18@102534 by Michael Rigby-Jones

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{Quote hidden}

       Normal speed I2C = 100Khz = 10us per bit, fast mode 400KHz = 2.5us
per bit.  In that time your state machine will have to decode the current
state of the lines, compare to the previous state and the state of the slave
in general (e.g if it has just been addressed, or is waiting for a start bit
etc).  If you have just received a byte, that will need to be stored
somewhere etc..etc.

       Basically an I2C software slave is orders of magnitude more complex
than a simple master, and timing is absolutely critical.  As Bob said, a
timer tick interrupt under DOS could be enough to stop this working
reliably.  Irrespective, this will need a reasonably fast machine.

       Even using clock stretching to slow the master dosen't help matters
much, as the state machine still has to work fast enough to be able to hold
the clock low before the master releases it.

       If your master if running at a substantialy slower speed, or if you
use some hardware for start/stop detection, then the task gets much easier.

       Several years ago I started writting a bus analyser that worked in a
non-real time way.  Basically it was a logic analyser, storing the state of
the lines into a large array, sampling as fast as possible.  Once the array
was full, the software decoded the states of the SCL and SDA lines through a
state machine.  It worked, kinda, but as there was no way of synchronising
that start of the data gathering to a start bit on the bus, it was all a bit
hit or miss was to wether you actually caught anything.  The next
improvement would be a simple latch on the port to detect a start condition,
and then start logging.  Dosn't know what happened to it, probably gathering
dust in a box of floppies up in the loft somewhere!

       The bottom line is, I'm sure it's possible to do, I just don't think
it's as easy as you do.

       Regards

       Mike

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2001\05\18@102825 by Bob Ammerman

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> No i'm talking about a slave, which should not
> be hard to do at all. Why do you see such a problem??
> :o)
> -Roman

Because timer interrupts can drag you away from your code for too long.

Bob Ammerman
RAm Systems
(contract development of high performance, high function, low-level
software)

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2001\05\19@105748 by Peter L. Peres

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> back of the envelope bus analyzer design

Well if you go parallel port like I did the key parts are a CD4094 and two
flipflops (one D one RS). I think that I got it down to 5 packages. You
may do it with or without a counter depending on the number of words to be
transmitted per packet. Without double buffering on parallel data the PC
needs to be pretty snappy to read it in.

The other option is a Scenix monitoring the lines while running at 100MHz
and doing serial (512K) or other forwarding to the PC.

Peter

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