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'[PIC]: Howto make 0-50 hz into 0-400 ?'
2001\08\21@143641 by Patrick J

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A friend of mine asked if I couldent help him convert a 0-50 Hz squarewave signal
to 0-400 Hz. The application is to adapt his RPM display 0-400 hz to 0-50 Hz.
The solution doesnt haveto be 100% exact.

I am not sure howto do this. The only idea I have so far is to use a PIC and measure
the 0-50 Hz signal then multiply the result by 8 and output the result somehow as
a squarewave signal...

Any suggestions most welcome :-)

/PJ

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2001\08\21@151848 by mike

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On Tue, 21 Aug 2001 20:37:41 +0200, you wrote:

>A friend of mine asked if I couldent help him convert a 0-50 Hz squarewave signal
>to 0-400 Hz. The application is to adapt his RPM display 0-400 hz to 0-50 Hz.
>The solution doesnt haveto be 100% exact.
>
>I am not sure howto do this. The only idea I have so far is to use a PIC and measure
>the 0-50 Hz signal then multiply the result by 8 and output the result somehow as
>a squarewave signal...
>
>Any suggestions most welcome :-)
>
>/PJ
..or build a circuit that generates 8 pulses on each input edge - you
could probably do this with a 4017 CMOS counter.
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2001\08\21@161444 by Spehro Pefhany

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At 08:37 PM 8/21/01 +0200, you wrote:
>A friend of mine asked if I couldent help him convert a 0-50 Hz squarewave
signal
>to 0-400 Hz. The application is to adapt his RPM display 0-400 hz to 0-50 Hz.
>The solution doesnt haveto be 100% exact.
>
>I am not sure howto do this. The only idea I have so far is to use a PIC
and measure
>the 0-50 Hz signal then multiply the result by 8 and output the result
somehow as
>a squarewave signal...
>

- Could the timebase of the RPM display be modified by 8:1 ?

- Is the range of speeds and rate of change relatively narrow and slow
respectively
 (use a PLL with an 8:1 divider in the feedback, eg. 4046, 4040).

- create some pulses on each edge of the income waveform (4 on each, say).
I think
 this could be done with a couple of CMOS gate packages (quad XOR and ST
inverter) and
 4 resistors + 4 capacitors.

Best regards,
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2001\08\21@161649 by Patrick J

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>..or build a circuit that generates 8 pulses on each input edge - you
>could probably do this with a 4017 CMOS counter.

hmm, I had some wild idea about doing that.. but wonderd howto make
the 8 pulses come evenly spaced and still not overlap into next 50 hz cycle
if the pulses are too far apart it will still be dong pulse 7 or 8 when next
50 hz pulse comes.
Tho you got me thinking.. maybe theres no need to have the pulses evenly
spaced but just fire 8 times as fast as it can take it basically - should work.

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2001\08\21@170924 by Giles Honeycutt

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Patrick,
I would suggest you stay analog, so not to induce other things like a block
of pulses and a gap.  That could have all kinds of results depending on how
your display unit works.
Think about a frequency to voltage then go from voltage to frequency.  This
way you can tweak in what ever multiplier you want by adjusting the 2
converters.

Best regards,
Giles

{Quote hidden}

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2001\08\21@173155 by cision Electronic Solutions

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Use Spehro's PLL idea with an 8-bit counter in the feedback loop.  Your
signals are slow enough that it should be able to maintain good lock and
provide evenly spaced pulses.  Take a look at a 4046.

{Original Message removed}

2001\08\21@194546 by steve

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> >..or build a circuit that generates 8 pulses on each input edge - you
> >could probably do this with a 4017 CMOS counter.
>
> hmm, I had some wild idea about doing that.. but wonderd howto make
> the 8 pulses come evenly spaced and still not overlap into next 50 hz
> cycle if the pulses are too far apart it will still be dong pulse 7 or
> 8 when next 50 hz pulse comes. Tho you got me thinking.. maybe theres
> no need to have the pulses evenly spaced but just fire 8 times as fast
> as it can take it basically - should work.

There's probably no reason that your output can't lag behind the
input by one cycle. I doubt it is something that the user would
notice. That means you can time one cycle, divide the time by
eight and generate evenly spaced pulses while you time the next
incoming cycle. If the incoming frequency varies by more than 1/8
you have a theoretical problem (you haven't finished sending the
last lot before you need to start over). Again, in practical terms,
who cares as long as you are looking for a frequency output, not an
absolute number of pulses.
The times are relatively long so it would be fairly simple to
implement as a couple of software timing loops in a 12C508 and
absolute frequency isn't an issue so the internal RC oscillator
would be fine.

Steve.


======================================================
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TLA Microsystems Ltd         Microcontroller Specialists
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Auckland, New Zealand        ph  +64 9 820-2221
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2001\08\21@235938 by Patrick J

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The PLL suggestions seems tricky. I remember a thread about
some major PLL-problems a few weeks back... Ill take a quick
look at it just to see whats involved :-)

The f/v and v/f method is one nice way.. no PIC tho ! ;-)

First I'll try to just send out 8 fast pulses for each 0-50 hz pulse
if that doesnt work. I think i'll go for this suggestion.
It doesn't sound simple to program at all, but hopefully doable :-)
It will be done in a F877 since I have a few of those.

Indeed all nice suggestions !
thanxs guys

{Quote hidden}

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2001\08\22@090629 by Olin Lathrop

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> The PLL suggestions seems tricky. I remember a thread about
> some major PLL-problems a few weeks back... Ill take a quick
> look at it just to see whats involved :-)

I think an analog phase locked loop might be a bit tricky here due to the
large dynamic range of the frequencies it would have to lock to.  However, a
PIC based digital PLL-like algorithm looks pretty straight forward.

The algorithm has three main parts, an input pulse detector, and output
pulse generator, and a output pulse error counter.  Whenever an input pulse
is detected, the pulse error counter is incremented by the number of output
pulses desired for that input pulse - 8 in your case.  Whenever an output
pulse is generated, the counter is decremented by one.  Output pulses are
generated from a free running pulse generator that has an adjustable period
value.  The error counter is low pass filtered and used to nudge the period
in the right direction.  For stability, you may want to take the derivative
of the low pass filtered error counter into account when nudging the output
pulse period.

Note that none of this requires accurate measurement of the frequencies.
You can do all this easily without a CCP module.  The oscillator frequency
also doesn't matter as long as it's fast enough to allow for the necessary
crunch power, which isn't much.  In fact, this looks like a perfect
application for a 12C508A running on its internal RC oscillator.  At 4MHz
clock you still have over 1200 instructions per half period of the highest
output frequency (400Hz).


********************************************************************
Olin Lathrop, embedded systems consultant in Littleton Massachusetts
(978) 742-9014, olinspamspam_OUTembedinc.com, http://www.embedinc.com

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2001\08\22@114010 by cision Electronic Solutions

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No problem with a digital PLL, Olin, this is a PIClist after all ;-).  My
concern was with converting a 0-50Hz signal into a 0-50Hz burst signal (see
below).  I still think he should use a PLL, analog or digital, to make the
conversion.  Either approach will require special consideration for dc, but
it would be easier to program the PIC for that.

" hmm, I had some wild idea about doing that.. but wondered how to make
the 8 pulses come evenly spaced and still not overlap into next 50 hz cycle
if the pulses are too far apart it will still be dong pulse 7 or 8 when next
50 hz pulse comes.
Tho you got me thinking.. maybe theres no need to have the pulses evenly
spaced but just fire 8 times as fast as it can take it basically - should
work."

{Original Message removed}

2001\08\22@160526 by Peter L. Peres

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Find out what the highest indicated RPM on that instrument is and then
program a PIC to output eight pulses for each one pulse it receives. The
PIC does not need to know the frequency. The induced error will be small
enough imho.

The other option is to program a software PLL in the PIC that runs on the
8th harmonic of the input. This will nix the error but may be more
difficult for you.

I assume that you'll be using a 12C508 on internal RC clock ;-).

Peter

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2001\08\22@211043 by Patrick J

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hmm, I just got another idea ...
How about i measure the input-freq and output it
using the PWM output ? Could the freq of the pwm
be changed/scaled 8x ?
As in always have a 50% pwm, but change the freq.

(I will use use a PIC16F877)

About PLL:
I know that a PLL is used to lock on to a special freq
but everyone here seems to agree on that it can be used
to multipy by 8 ?!?


/PJ

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2001\08\23@005420 by cision Electronic Solutions

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Patrick J wrote:
About PLL:
I know that a PLL is used to lock on to a special freq
but everyone here seems to agree on that it can be used
to multipy by 8 ?!?


Patrick,
A phase locked loop is usually used to lock one frequency to another.
Consider a simple block diagram of a classical analog PLL.  It will have a
phase comparison block, sometimes in phase or in quadrature (90 degrees out
of phase), which produces an error signal.   This error signal indicates
whether the feedback signal edge lags or leads the original signal, i.e.,
whether the feedback signal is a little too fast or a little too slow
relative to the original.  This error is fed into a filter block - the loop
filter - whose output is put into a block containing the voltage to
frequency converter (VtoF).  The output of the voltage to frequency
converter can either be used directly as the feedback to the phase
comparison block, or it can be fed into a counter, say a divide by eight,
and the output of the counter fed back to the comparison block.  But we know
that for the comparison block to work, the comparison frequencies need to be
the same.  The only way for them to be the same is if the output of the VtoF
is exactly 8 times higher frequency than the original.  Tap off the VtoF to
get a frequency exactly 8 times higher than the original.  The biggest
problem with your design is the very low frequency part.  Getting an analog
VtoF to operate that low would be difficult.  You could try a much larger
divide ratio and tap out at the appropriate counter output or you could do
the PLL in software.

Today most low frequency PLLs are done in software, but you will see very
high frequency PLLs used in time measurement circuits for mass spectroscopy
time of flight measurements, in fiber optic communication systems, or
anywhere that precise time locked signals are required.  For example, most
DSP's use PLLs to multiply the oscillator to get 2 or 4 times internal clock
speeds.

Attached is a link to the CD4046 PLL.  They will do a much better job
explaining its operation.  Yes, many companies are obsoleting it, but look
at the various 74XXX4046 devices available, then tell me its obsolete.

http://www.fairchildsemi.com/pf/CD/CD4046BC.html

Regards,
Ed

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2001\08\23@090703 by Olin Lathrop

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> About PLL:
> I know that a PLL is used to lock on to a special freq
> but everyone here seems to agree on that it can be used
> to multipy by 8 ?!?

A PLL (phased locked loop) locks the output of its own oscillator to an
incoming signal.  It does this by adjusting the frequency of its own
oscillator from the phase error between the two signals.  Now suppose the
oscillator was run thru a counter to divide its frequency by N before being
phase compared to the input signal.  If oscillator/N is phase locked to the
input, then oscillator must be input * N.

I've left out lots of details, especially regarding implementation and
limitations, but I'm sure there is LOTS of stuff on PLLs out there on the
web.


********************************************************************
Olin Lathrop, embedded systems consultant in Littleton Massachusetts
(978) 742-9014, KILLspamolinKILLspamspamembedinc.com, http://www.embedinc.com

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2001\08\23@112058 by Scott Dattalo

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On Thu, 23 Aug 2001, Olin Lathrop wrote:

> > About PLL:
> > I know that a PLL is used to lock on to a special freq
> > but everyone here seems to agree on that it can be used
> > to multipy by 8 ?!?
>
> A PLL (phased locked loop) locks the output of its own oscillator to an
> incoming signal.  It does this by adjusting the frequency of its own
> oscillator from the phase error between the two signals.  Now suppose the
> oscillator was run thru a counter to divide its frequency by N before being
> phase compared to the input signal.  If oscillator/N is phase locked to the
> input, then oscillator must be input * N.
>
> I've left out lots of details, especially regarding implementation and
> limitations, but I'm sure there is LOTS of stuff on PLLs out there on the
> web.

Multiplication by 8 is especially easy. If I were to implement this in
software I'd go about it like this:

1) Measure the time between rising edges of the ~50Hz signal. This will
give you the period for one cycle.

2) Filter the measured period with a recursive low pass filter of the type
that's been discussed before here.

3) Divide the filtered 50Hz period by 8 (i.e. shift right 3) and you'll
have the period of the ~400Hz wave. Now, you'll actually want to divide by
16 instead of 8 so that you can obtain the time for the "half-period" and
thus know how long the ~400hz wave is high/low.


The challenge is to merge these three operation into one seamless (or seem
less) isochronous algorithm.

While I don't have time to fill in the details, I can suggest a few
snippets:

Capture rising edges:



main_loop_start:

   ; last_state =  last sampled value

   movf   IOPORT,W     ;sample ~50hz waveform
   andlw  IOMASK       ;get only the bit of interest
   xorwf  last_state,W ;compare to last sample (W=1 if different)
   xorwf  last_state,F ;save this sample as the old value
   andwf  last_state,W ;If there's a difference and it's high
                       ; then we found a rising edge
   skpnz
    goto  L1

 ; filter accumulated 50 hz period...
 ; clear 50 hz period counter

ML1:   ; re-entry point for isochronous delay

;main isochronous loop flow
     .
     .
     .


   goto   main_loop_start


L1:
   incf   period_50Hz_low,f
   skpnz
    incf  period_50Hz_high,f

;   skpnz      ;if 24 bit counter is needed then uncomment this
;    incf  period_50Hz_real_high,f

  ;delay an amount equal to the time required to filter
  ;the period.

    ...

    goto   ML1    ;re-enter flow of isochronous loop


-----------------

; shift fperiod (filtered 50Hz period right 4)

   swapf   fperiod_hi,W   ;Shift high byte right 4
   movwf   p400_hi        ;and put it into 400Hz period counter
   andlw   0xf0           ;but upper nibble goes into low byte
   movwf   p400_lo
   xorwf   p400_hi,f      ;Clear upper nibble of high byte

   swapf   fperiod_lo,W   ;shift low byte right 4
   andlw   0x0f           ;put the high nibble into
   iorwf   p400_lo,f      ;the low nibble of p400

;
; note that this will leave the upper nibble of p400_hi
; equal to zero and that the low nibble of fperiod is thrown away



decrementing the 400hz period counter:
;-------------

    movlw   1              ;subtract 1 from the 400hz half-period
    subwf   p400_lo,f      ;counter. The carry gets cleared when
    skpnc                  ;count underflows. Note that this is
     subwf  p400_hi,f      ;an extra count that may have to
                           ;be accounted for

    movwf   IOPORT,w       ;read current 400hz waveform state
    xorlw   b400HZ_OUTPUT  ;invert it

    skpc                   ; did counter reach zero?
     movwf   IOPORT        ;yep, so write new state.


Out of time...

Scott

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2001\08\23@120759 by Olin Lathrop

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> For example, most
> DSP's use PLLs to multiply the oscillator to get 2 or 4 times internal
clock
> speeds.

As does the PIC 18xxx series, by the way.


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Olin Lathrop, embedded systems consultant in Littleton Massachusetts
(978) 742-9014, TakeThisOuTolinEraseMEspamspam_OUTembedinc.com, http://www.embedinc.com

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