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'[PIC]: High speed sampling --> data storage'
2001\09\24@113306 by Wade Carpenter

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Hello everyone!

I have run across the problem that I need to do some high speed sampling.  High speed I mean in terms of the PIC.  Running my 876 at max speed of 20MHz, I have not too much time to do things if I want to sample at 500Khz.  And an analog signal at that.  The good part is, I only need low analog resolutions (maybe 4-bits) so I was going to build a flash ADC from discretes; 4 bit parallel ouput faster than I can handle.

But I have to read continuously 128x128 pixels, store it in memory, and THEN transmit it via very slow serial to a PC (wireless!).  
Now my PIC has 368 bytes of RAM - slight conflict of interest here.

So I was considering a 16K SRAM (128x128 = 16K).  Does anyone have any suggestions?? Would this be easy enough to implement? Ie connect my 4bit adc on port A, read the whole thing and write it parallel via port B to an SRAM.. that should take less than my 5 allowed instructions =)  I hope!! unless the SRAM is really complicated.. but I hope not..  I only really know of SRAM and DRAM, but I know that DRAM will not do the trick =) No chance to refresh anything here!

If you have any ideas, please let me know!  Your efforts are much appreciated =)


Thanks so much!

Wade Carpenter

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2001\09\24@121538 by M. Adam Davis

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Hmmm...  5 instructions?

You might be better off going with an 18c chip, which will not only give
you 2x the speed (40MHz @ 10MHz clock), but you can expose the
data/address bus and hook your ram directly to the chip...  Of course,
the whole design would end up being 3 or more chips.

The ideal solution is to hook both the pic and the A/D to the sram.  The
PIC then simply tells the A/D to get a sample, and the tells the sram to
record it.  When it needs to send it, it'll read it from the sram at a
more leisurely pace.

So five instructions is good:

Start sample (probably raise a pin)
Start write to sram(probably another pin)
Lower both pins (increment sram address)
Loop (two cycles minimum)

Since the timing is fixed you could even use a few other chips that
raise and lower the pins a fixed amount of time after raising one pin.
Then all you have to do is send out a pulse at 500Hz for 16384.  This
assumes that you use another chip that increments the address for the
sram, since you'd have to write two ports to address the whole ram.

This requires some external logic and timers, but is really one of the
only practical ways to get  that kind of performance from this chip.

-Adam

Wade Carpenter wrote:

{Quote hidden}

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2001\09\24@122814 by uter van ooijen & floortje hanneman

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So I was considering a 16K SRAM (128x128 = 16K).  Does anyone have any
suggestions?? Would this be easy enough to implement? Ie connect my 4bit adc
on port A, read the whole thing and write it parallel via port B to an
SRAM.. that should take less than my 5 allowed instructions =)  I hope!!
unless the SRAM is really complicated.. but I hope not..  I only really know
of SRAM and DRAM, but I know that DRAM will not do the trick =) No chance to
refresh anything here!

Consider using an SX? More MIPS available (roughly 50 versus 5), DRAM might
even be useable.

Wouter van Ooijen

Van Ooijen Technische Informatica: http://www.voti.nl
Jal compiler for PIC uC's:  http://www.xs4all.nl/~wf/wouter/pic/jal

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2001\09\24@124434 by Mike Hardwick

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Wade,

I suggest a FIFO memory, e.g. Cypress CY7C462/472 or similar. Commodity
FIFOs are 9 bits wide, so, if you're handy with logic design, you might
consider storing two samples per data word.

Also, I would try to use a commodity ADC before making my own. I think
there are inexpensive and fast 6~8 bit ADCs out there. You can just discard
the unwanted LSBs...

Mike Hardwick
Decade Engineering


>I have run across the problem that I need to do some high speed sampling.
High speed I mean in terms of the PIC.  Running my 876 at max speed of
20MHz, I have not too much time to do things if I want to sample at 500Khz.
And an analog signal at that.  The good part is, I only need low analog
resolutions (maybe 4-bits) so I was going to build a flash ADC from
discretes; 4 bit parallel ouput faster than I can handle.
>
>But I have to read continuously 128x128 pixels, store it in memory, and
THEN transmit it via very slow serial to a PC (wireless!).
>
>Now my PIC has 368 bytes of RAM - slight conflict of interest here.
>
>So I was considering a 16K SRAM (128x128 = 16K).  Does anyone have any
suggestions?? Would this be easy enough to implement? Ie connect my 4bit
adc on port A, read the whole thing and write it parallel via port B to an
SRAM.. that should take less than my 5 allowed instructions =)  I hope!!
unless the SRAM is really complicated.. but I hope not..  I only really
know of SRAM and DRAM, but I know that DRAM will not do the trick =) No
chance to refresh anything here!

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2001\09\24@142123 by Byron A Jeff

face picon face
On Mon, Sep 24, 2001 at 12:13:37PM -0400, M. Adam Davis wrote:
> Hmmm...  5 instructions?
>
> You might be better off going with an 18c chip, which will not only give
> you 2x the speed (40MHz @ 10MHz clock), but you can expose the
> data/address bus and hook your ram directly to the chip...  Of course,
> the whole design would end up being 3 or more chips.
>
> The ideal solution is to hook both the pic and the A/D to the sram.  The
> PIC then simply tells the A/D to get a sample, and the tells the sram to
> record it.  When it needs to send it, it'll read it from the sram at a
> more leisurely pace.
>
> So five instructions is good:
>
> Start sample (probably raise a pin)
> Start write to sram(probably another pin)
> Lower both pins (increment sram address)
> Loop (two cycles minimum)

That's the right idea. At 500KHz there more than enough time for a 20 Mhz
chip to drive everything. There's 100 instruction cycle time in that interval.
That's enough time to sample the A/D and write it to the ram. So probably it
wouldn't be necessary to connect the A/D directly to the RAM. It may be a good
idea however to supply external counters to the ram for pin efficiency. It
would only require a 4 bit control interface and the 8 bit data interface.
The 4 control pins are CS, WE (R/W), clear address counters, and increment.
Use two HCT393 ripple counters and you have a quick sequential interface
to the RAM.

>
> Since the timing is fixed you could even use a few other chips that
> raise and lower the pins a fixed amount of time after raising one pin.
>  Then all you have to do is send out a pulse at 500Hz for 16384.  This
> assumes that you use another chip that increments the address for the
> sram, since you'd have to write two ports to address the whole ram.
>
> This requires some external logic and timers, but is really one of the
> only practical ways to get  that kind of performance from this chip.

Not really. With 100 instruction cycles between samples, a 20 Mhz chip will
be more than enough to handle the job...

BAJ
{Quote hidden}

Is my math wrong? The instruction clock at 20 Mhz is 5 MIPS. So each
instruction cycle is 200ns. Right? 500Ksamples occurs at a rate of 1 every
20 uS. So 20 uS/.2 uS -> 100. So there's actually 100 instructions available
between each sample.

Did I miss something?

BAJ

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2001\09\24@142951 by Byron A Jeff

face picon face
> > Wade Carpenter wrote:
> >
> > >Hello everyone!
> > >
> > >I have run across the problem that I need to do some high speed sampling.  High speed I mean in terms of the PIC.  Running my 876 at max speed of 20MHz, I have not too much time to do things if I want to sample at 500Khz.  And an analog signal at that.  The good part is, I only need low analog resolutions (maybe 4-bits) so I was going to build a flash ADC from discretes; 4 bit parallel ouput faster than I can handle.
> > >
> > >But I have to read continuously 128x128 pixels, store it in memory, and THEN transmit it via very slow serial to a PC (wireless!).
> > >
> > >Now my PIC has 368 bytes of RAM - slight conflict of interest here.
> > >
> > >So I was considering a 16K SRAM (128x128 = 16K).  Does anyone have any suggestions?? Would this be easy enough to implement? Ie connect my 4bit adc on port A, read the whole thing and write it parallel via port B to an SRAM.. that should take less than my 5 allowed instructions =)  I hope!! unless the SRAM is really complicated.. but I hope not..  I only really know of SRAM and DRAM, but I know that DRAM will not do the trick =) No chance to refresh anything here!
> > >
>
> Is my math wrong? The instruction clock at 20 Mhz is 5 MIPS. So each
> instruction cycle is 200ns. Right? 500Ksamples occurs at a rate of 1 every
> 20 uS. So 20 uS/.2 uS -> 100. So there's actually 100 instructions available
> between each sample.
>
> Did I miss something?

Duh. I missed a zero. 500KSamples is one every 2 uS. So there are 10
instructions inbetween each sample. That should be enough time to transfer the
data directly from the A/D to the ram, restart the ADC, and increment the RAM
address.

Does the A/D have a Data valid output? You may be able to use it to autowrite
to the RAM....

BAJ

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2001\09\24@174957 by Olin Lathrop

face picon face
> That's the right idea. At 500KHz there more than enough time for a 20 Mhz
> chip to drive everything. There's 100 instruction cycle time in that
interval.

Actually only 10 instructions.

> That's enough time to sample the A/D and write it to the ram. So probably
it
> wouldn't be necessary to connect the A/D directly to the RAM. It may be a
good
> idea however to supply external counters to the ram for pin efficiency. It
> would only require a 4 bit control interface and the 8 bit data interface.
> The 4 control pins are CS, WE (R/W), clear address counters, and
increment.
> Use two HCT393 ripple counters and you have a quick sequential interface
> to the RAM.

Yes, this would have been reasonable if there were 100 instructions
available, but not with only 10 instructions.


********************************************************************
Olin Lathrop, embedded systems consultant in Littleton Massachusetts
(978) 742-9014, spam_OUTolinTakeThisOuTspamembedinc.com, http://www.embedinc.com

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2001\09\24@223442 by Drew Vassallo

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You could, of course, go to an SX chip to try to get the 100 instructions
back, or try a 40MHz PIC to give you a little more time (20 cycles).

--Andrew

_________________________________________________________________
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2001\09\25@172555 by Peter L. Peres

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You don't need to refresh DRAM while you are reading or writing from/to
it, just make sure your operations visit a whole DRAM page within the
required time (i.e. 128 or 256 or 512 operations in a row within 4 or 8
msec - easy).

A quick and sneaky way out of the pin maze for a fast data sampler is a
FIFO RAM combined with continuous flash A/D like HM1175 and friends or
higher. The FIFO has only write, read, clock, and reset pins beyond the
data path, which is 4 or 8 or 16 bits wide. All you need to do is to
connect the AD clock and the FIFO clock together and supply /WR to the
FIFO with correct phase (every clock cycle). This yields a 40MSPS sampler
(using HM1175 etc). There are other options. The address counter is in the
FIFO and it is reset at the beginning.

The only problem is getting hold of FIFOs. They are used in some high end
network and video cards and some are unbelievably fast. Try to find
something suitable.

Peter

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2001\09\26@034338 by Alan B. Pearce

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>The only problem is getting hold of FIFOs. They are used in some high end
>network and video cards and some are unbelievably fast. Try to find
>something suitable.

The Integrated Technology IDT72xx range is quite readily available from RS
Components. These come as 9 bit wide devices in various depths, and are
cascadable for length and width.

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2001\09\26@091007 by Octavio P Nogueira

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Do you know where I can buy some of HM1175?
Who makes it?

Friendly Regards

Octavio Nogueira
===================================================
.....nogueiraKILLspamspam@spam@propic2.com                  ICQ# 19841898
ProPic tools - low cost PIC programmer and emulator
http://www.propic2.com
===================================================

{Original Message removed}

2001\09\27@050835 by Peter L. Peres

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> HM1175

Harris. Also made by Sony and others. It is a 'industry standard' part,
i.e. everyone makes it. You do not have to use this chip. Look for 'flash
A/D' in a Digi-Key catalog or something like that. I was wrong about the
type number for Harris - it is HI1175. Compatible chips have a different
prefix and the same number usually. Sony's is CXA1175 afair. There are
better choices now though. Understanding the data sheet of the 1175 will
likely help you to use other similar chips. The 11775 is 8 bit bus
oriented.

Peter

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'[PIC]: High speed sampling --> data storage'
2001\10\04@022949 by Wade Carpenter
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Hi everyone!!

Thanks so much to everyone who made all the suggestions on this topic.
We're almost to implementation now, so I'll have to let you guys know how it
went.. And of course, all my source code will be available once it works, so
if anyone wants to use a Gameboy camera for a project, you might be able to
after all this is done.

So here's the general operation for what I'm planning to do.

(1) Startup sequence:  Clock in 8 registers (8bits each) serially in
succession into the camera. This sets up the various modes of operation.
Then you have to trigger it once to begin the exposure, wait for the
exposure time (tricky part here, especially if not clocking at the spec'd
500kHz!) and then start clocking out the analog values corresponding to the
pixels.

In case anyone has forgotten, the problem is to read and store 128x128
analog -> digital values for later sending to the PC.

(2) For clocking out the analog values, we set up some kind of DMA-type
system.  128x128 = 16384 = 2^14, so 14 bits of counter hardware will do
nicely to auto-increment the SRAM address.  The SRAM is a 70ns 256K (32Kx8)
chip.  We're using the only National A/D converter in a DIP package (that we
could find) that runs at less that 2us (500kHz) so that we can have the full
bit-accuracy of the ADC (although it's probably not necessary, anyway).  So
we set up the PWM on the PIC to run this so-called DMA system. Hopefully we
can get some kind of overflow signal from the counter (maybe 15 bits of
counter, in that case).  At 20MHz, the PWM happily (register = 9, duty cycle
reg = 5) runs at 500kHz, 50% to do all our clocking.  Then that overflow
signal, we can attach to an input, and poll, so that we know when to stop
sampling and send the data to the PC.

Well, if anyone has any questions about this, just let me know!!

I was hoping to implement a FIFO-system, but I couldn't find a decent FIFO
for the application.. 16Kx8 is a big FIFO, apparently, and availability in
DIP parts for any kind of memory seems quite poor (unless you want to pay
around $50CDN).

Thanks again for all the help in the past!

- Wade

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