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'[PIC]: GIE Disables, answer from m-chip ..( I thin'
2001\02\21@082452 by o-8859-1?Q?K=FCbek_Tony?=

found this in one if the hi-tech forums, I hope
it's ok for me copying it and re-posting in this
forum, as there have been several discussions regarding
the use of loops when disabling global irq, and
people seems to differ:

My qustion to Microchip:

Dear sir,

In application note AN576 the bug "GIE=0 is not reliable and should be
placed in a loop" is
explained. Has this issue been solved for the newer 16Fxxx chips or does the
necessity of a loop to reliable clear the Global interrupt still holds?


Paul Nijdam.

Microchip's reply:


The GIE issue is not a 'bug' in the part it relates more to an operational
consideration when the GIE bit is handled in software to disable the
interrupt system and the fact that during execution of that operation it is
possible for an interrupt to occur. The nature of the MCU core operation
means that whilst the current instruction is flowing through the device an
asynchronous interrupt can occur. The result of this is that the processor
will vector to the ISR disable GIE, handle the Interrupt and then enable
GIE again. The result of this is of course that the instruction to disable
GIE has been overridden by the processor vectoring to the interrupt and
disabling then enabling the interrupt. This is a very real possibility and
AN576 is explaining a method to ensure that, in the specific instance where
you wish to disable GIE in software during normal execution that your
operation has not been negated by the very action you wish to stop.

The app note is related to the disabling of GIE in software. The disabling
and re-enabling of GIE when an interrupt occurs is performed in hardware by
the processor and the execution of the RETFIE instruction. The GIE check is
a safeguard to ensure your expected/desired operation has occured and your
program can then operate as expected/desired without the unexpected
occurence of an interrupt.

This issue remains on the current range of parts since it is related to the
operation of the core when the user wishes to take control of the interrupt
system again.

Best Regards,

UK Techhelp

Tony Kübek, Flintab AB            

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