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'[PIC]: Critique this Circuit/PCB ?'
2002\12\02@183412 by William Chops Westfield

face picon face
This is a 16C57 with some transistors, driving 8 digits worth of
multiplexed LED display, with the intent of serving as a generic
"serial LED" display, or for any smallish clock-like circuit.
Should be at:
       http://www.geocities.com/westfw/electronics/pic-display.zip

(This is an Eagle schematic and board file, all zipped up.)
I'm interested in suggestions of all sorts, from "you really need some
reset circuitry" to "the patterns the traces make are ugly" and/or "don't
you think it would have been smarter to start with a standard sized board
of some sort instead of picking random dimensions?"

Thanks
Bill W

(yeah, I know 16c57s are dinosaurs.  But between Ebay and piclist, I now
have quite a lot of them to do SOMETHING with.  Other suggestions are
welcome, too...)

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2002\12\03@081808 by Olin Lathrop

face picon face
>         http://www.geocities.com/westfw/electronics/pic-display.zip
>
> (This is an Eagle schematic and board file, all zipped up.)
> I'm interested in suggestions of all sorts,

* Nice job on the schematic symbols for the 4 digit displays.  Did you
make those yourself?

* Either smash a symbol and move its label or don't cram things so close
together that the labels can't be read.  Neatness counts.  Use more sheets
if you have to.

* The crystal caps should go to GND, not VDD, although it will probably
work fine this way.

* A bunch of parts don't have values, like C1, C2.  Again neatness and
attention to detail count.

* I don't follow what's going on with the fat traces (polygon?) on the top
layer around the two displays.  This seems to be overlaying a whole row of
pads.  There are several instances of this sort of thing.

* Don't let the silkscreen get onto the pads.  It can act like a solder
mask.


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2002\12\03@115249 by Florian Voelzke

picon face
Olin Lathrop wrote:
> * I don't follow what's going on with the fat traces (polygon?) on the top
> layer around the two displays.  This seems to be overlaying a whole row of
> pads.  There are several instances of this sort of thing.

Click on "ratsnest" so eagle can process the polygons. The resulting
ground-plane will have the distance to any other signal as stated in the
design rules.

That's the common way to make power planes which fill unused space on
any layer you like...

Florian Voelzke

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2002\12\03@121909 by Olin Lathrop

face picon face
> Click on "ratsnest" so eagle can process the polygons. The resulting
> ground-plane will have the distance to any other signal as stated in the
> design rules.
>
> That's the common way to make power planes which fill unused space on
> any layer you like...

Yes, that's what I expected too.  When I ran RAT only one are turned into
a plane.  That was over by the processor.  The areas by the displays did
not do that, which is why I'm not sure what is going on.


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2002\12\03@123009 by Florian Voelzke

picon face
Olin Lathrop wrote:
>>Click on "ratsnest" so eagle can process the polygons. The resulting
>>ground-plane will have the distance to any other signal as stated in the
>>design rules.
>>
>>That's the common way to make power planes which fill unused space on
>>any layer you like...
>
>
> Yes, that's what I expected too.  When I ran RAT only one are turned into
> a plane.  That was over by the processor.  The areas by the displays did
> not do that, which is why I'm not sure what is going on.
>

Strange, because it worked for me as described.

Nice ground planes above the PIC, displays and at the PCB border. And a
plane on the bottom at the PCB border. All have minimum distance to
other signals.

(I use eagle 4.09r2)

Florian

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2002\12\03@140610 by Olin Lathrop

face picon face
> Strange, because it worked for me as described.
>
> Nice ground planes above the PIC, displays and at the PCB border. And a
> plane on the bottom at the PCB border. All have minimum distance to
> other signals.
>
> (I use eagle 4.09r2)

I've got exactly the same version, so I went back and looked at the board
again.  I reloaded the original file and did a RAT, and the planes did
show up correctly.  However, if you do a RIPUP on all the wires and then
RAT, only the plane by the processor shows up.  I don't know why.


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2002\12\03@154335 by William Chops Westfield

face picon face
   Yes, that's what I expected too.  When I ran RAT only one are turned into
   a plane.  That was over by the processor.  The areas by the displays did
   not do that, which is why I'm not sure what is going on.

Hmm.  That's odd.  They fill fine when I look at them.  I wonder if there's
something I have in my init files that isn't "sticky" in the .BRD file,
resulting in a "design rule conflict" or something.  I'll have to take
a closer look at that.

BillW

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2002\12\03@154343 by William Chops Westfield

face picon face
   > (This is an Eagle schematic and board file, all zipped up.)
   > I'm interested in suggestions of all sorts,

   * Nice job on the schematic symbols for the 4 digit displays.  Did you
   make those yourself?

Yes, I did.  Thanks!  (Unfortunately, they're not quite complete, as I
confirmed when actual parts reached my hands.  The symbols will get a bit
uglier when the missing pins get defined.  Sigh.)


   * Either smash a symbol and move its label or don't cram things so close
   together that the labels can't be read.  Neatness counts.  Use more sheets
   if you have to.

It's the freeware version, so I'm limitted to one sheet.  I have a "real
problem" with "density" vs readability, especially when it comes to text.
I used some of the DIN TTL symbols in another schematic, and they were HUGE
compared with (for instance) the PIC symbols.  For the resistors here, I
tried to delete most of the lables, but it seems that if you smash and
delete both name an value, you get unsmashed text back when you redisplay.
(I think there were some suggestions of moving the smashed text to
undisplayed layers on the Eagle newsgroups - I'll try that.)


   * The crystal caps should go to GND, not VDD, although it will probably
   work fine this way.

Yes, I started a discussion on that topic a while back.  Still, in this
case, I'm not sure I need to use VCC - that part of the schematics was
copied from a single-layer board where the crystal placement and wiring
was more critical.


   * A bunch of parts don't have values, like C1, C2.  Again neatness and
   attention to detail count.

Noted.

   * I don't follow what's going on with the fat traces (polygon?) on the top
   layer around the two displays.  This seems to be overlaying a whole row of
   pads.  There are several instances of this sort of thing.

As a signal-bearing polygon, these automatically "retract" to the isolation
distance (relatively large on my boards) from all other signals when you do
a rats-nest operation to "fill" the polygons. (The 'filled' status of
polygons doesn't seem to get saved, though.)  The top-layer polygon you
mention does have a different line width than the other polygons for no good
reason, though.  I'm usually not very careful about fine placement of the
polygon, since the 'real' copper gets computed.  Should I be?


   * Don't let the silkscreen get onto the pads.  It can act like a solder
   mask.

Ah.  I thought I was careful with this, but I see problems over by the
connectors for inbound signals.  I should probably rework those "packages",
since the current text placement is particularly badly suited toward the
obviously-shaped arrays of "wires."

BillW

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2002\12\03@160754 by Olin Lathrop

face picon face
>     * Don't let the silkscreen get onto the pads.  It can act like a
solder
>     mask.
>
> Ah.  I thought I was careful with this, but I see problems over by the
> connectors for inbound signals.  I should probably rework those
"packages",
> since the current text placement is particularly badly suited toward the
> obviously-shaped arrays of "wires."

I noticed this especially on your resistors and even some surface mount
transistors.  Surface mount pads in particular need to be kept clear.  It
wasn't the label text, but rather the symbol.  In the case of the
resistors, it was the wire symbol extending from the body to halfway into
the pad.  The transistors seemed to have a silkscreen picture of a pad on
top of part of the pad.


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2002\12\03@192338 by William Chops Westfield

face picon face
   I've got exactly the same version, so I went back and looked at the board
   again.  I reloaded the original file and did a RAT, and the planes did
   show up correctly.  However, if you do a RIPUP on all the wires and then
   RAT, only the plane by the processor shows up.  I don't know why.

Ah hah!  The board has extra "wires" that connect the ground plane polygons
to the "real" ground traces.  If you rip up everything, those wires will get
deleted, and the polygons remain unfilled because they're not connected to
the signals that they're supposed to be connected to.  (You MIGHT get an
extra airwire to the polygon as well, but I doubt that you'd see it in the
mess, and i'm not sure...)  Unlike the groundplane near the PIC, which has
signal-bearing pins through it, the display groundplanes are "pure."

Now I'm curious as to why you did a "ripup all" as part of examining the
design?

BillW

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2002\12\04@051635 by William Chops Westfield

face picon face
> Don't let the silkscreen get onto the pads.  It can act like a solder mask.
:
> I noticed this especially on your resistors and even some surface mount
> transistors.  Surface mount pads in particular need to be kept clear.  It
> wasn't the label text, but rather the symbol.  In the case of the
> resistors, it was the wire symbol extending from the body to halfway into
> the pad.  The transistors seemed to have a silkscreen picture of a pad on
> top of part of the pad.

Those packages are from the standard Eagle libraries, and I think what
you're seeing is "extra" silkscreen pieces.  Eagle has an extra couple of
layers "tDocument" and "bDocument" that are designed to show up in the board
editor and in "Documentation" printouts, but NOT on the actual silkscreen
(which would have only tPlace, tNames, and tValues.  Or something like
that.)  "Fancy" library defintions (like the resistors) have part of the
lead drawn on tDocument (the part that overlaps the pad) and part on tPlace
(which mostly doesn't overlap pads.)  My display package has some pin names
drawn on tDocument that would be way too tiny to work on an actual
silkscreen.  It's a useful feature, although it makes the prospect of
developing libraries "for publication" a bit daunting.  There seem to be
quite a LOT of layers where SOME libraries have put SOMETHING that's
mostly incomprehensible.  Other layers (soldermask) seem more automatic.

BillW

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2002\12\04@075344 by Olin Lathrop

face picon face
> Ah hah!  The board has extra "wires" that connect the ground plane
polygons
> to the "real" ground traces.

I would have expected the polygons to be named with the signal name.  That
should have automatically connected them to the net of that name, at least
so I thought.

> Now I'm curious as to why you did a "ripup all" as part of examining the
> design?

Just curious and poking around.


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2002\12\04@080843 by Olin Lathrop

face picon face
> Those packages are from the standard Eagle libraries, and I think what
> you're seeing is "extra" silkscreen pieces.  Eagle has an extra couple
of
> layers "tDocument" and "bDocument" that are designed to show up in the
board
> editor and in "Documentation" printouts, but NOT on the actual
silkscreen
> (which would have only tPlace, tNames, and tValues.  Or something like
> that.)

Ah, that could explain it.  I turned on tPlace and did notice a bunch of
other layers came on automatically.  I didn't pay much attention to this
because I've never used tDocument before.  I don't like the Eagle
libraries for a variety of reasons, and my own libraries only use tPlace,
so I wasn't aware of this feature.  Sorry about the confusion.


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2002\12\04@081308 by Dave Tweed

face
flavicon
face
William Chops Westfield <.....billwKILLspamspam@spam@CISCO.COM> wrote:
> Olin wrote:
> > Don't let the silkscreen get onto the pads.  It can act like a solder mask.
> > :
> > I noticed this especially on your resistors and even some surface mount
> > transistors.  Surface mount pads in particular need to be kept clear.  It
> > wasn't the label text, but rather the symbol.  In the case of the
> > resistors, it was the wire symbol extending from the body to halfway into
> > the pad.  The transistors seemed to have a silkscreen picture of a pad on
> > top of part of the pad.
>
> Those packages are from the standard Eagle libraries, and I think what
> you're seeing is "extra" silkscreen pieces.  Eagle has an extra couple of
> layers "tDocument" and "bDocument" that are designed to show up in the board
> editor and in "Documentation" printouts, but NOT on the actual silkscreen
> (which would have only tPlace, tNames, and tValues.  Or something like
> that.)

It may be a non-issue anyway. Many PCB fabrication houses by default do
a logical "and" of the silkscreen with the soldermask, automatically
eliminating any silkscreen elements that fall off the edges of the
soldermask layer.

They have learned through experience that designers sometimes slip up
on this, and they'd rather produce usable boards than readable boards.
Automatic pick-and-place machines don't read the silkscreen anyway.

-- Dave Tweed

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