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'[PIC]: CAS/RAS - corrected'
2002\05\01@043320 by Jon Baker

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Erm.. and now I've woken up....

----- Original Message -----
From: "Jon Baker" <spam_OUTjonTakeThisOuTspamHAYSEED.NET>
To: <.....PICLISTKILLspamspam@spam@MITVMA.MIT.EDU>
Sent: Wednesday, May 01, 2002 9:02 AM
Subject: Re: [PIC]: CAS/RAS


> for cAS before  RAS:
>
CAS low
for counter=1 to n_rows
RAS low
wait
RAS high
next
CAS high

> > Does CAS go LOW, then RAS gets cycled for each ROM address, then CAS
> > goes HIGH again?
>
> I think that is a hidden refresh, and not all dram supports it.

Hidden refresh is a type of cas before ras refresh but differs in that it
can take place immediately after a data transfer and before cas is returned
high again. You can also pulse ras more than once before returning cas high
to do a burst refresh- hidden refresh has the addvantage that the data
presented on the bus after a read remains valid even though you are
refreshing the dram.

--
Jon Baker

I'll be quiet now.

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2002\05\01@184243 by Tony Nixon

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Jon Baker wrote:
>
> Erm.. and now I've woken up....

Cough gag splutter...Me too [yawn]

{Quote hidden}

I thought that may be the case. I used and modified the code that I
found on the PIClist about SIMM interfacing. It has a loop like this,
which I thought was a bit odd..

  for anotherCounter=1 to 32
   CAS low
   for counter=1 to 8
     RAS low
     wait
     RAS high
   next
   CAS high
 next

I guess it achieves the same thing though.

Many thanks

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Best regards

Tony

mICros
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2002\05\02@065257 by Jon Baker

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> Jon Baker wrote:

> > > for cAS before  RAS:
> > >
> > CAS low
> > for counter=1 to n_rows
> > RAS low
> > wait
> > RAS high
> > next
> > CAS high
>
"Tony Nixon" wrote:

{Quote hidden}

I find that a bit strange, I thought that the action of lowering the CAS
reset the internal address counter- so in your example ( if this is the
case ) only the first 1/32 of the memory would get refreshed. I'll see if I
can find a datasheet and get the definitive answer- but then, like Michael
said.. if its working, then its probably right :)

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2002\05\02@195621 by Tony Nixon

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Jon Baker wrote:
> >
> >    for anotherCounter=1 to 32
> >     CAS low
> >     for counter=1 to 8
> >       RAS low
> >       wait
> >       RAS high
> >     next
> >     CAS high
> >   next
> >
> > I guess it achieves the same thing though.
>
> I find that a bit strange, I thought that the action of lowering the CAS
> reset the internal address counter- so in your example ( if this is the
> case ) only the first 1/32 of the memory would get refreshed. I'll see if I
> can find a datasheet and get the definitive answer- but then, like Michael
> said.. if its working, then its probably right :)

I looked fairly hard around the web for a data sheet on the M5M44100
chips from Mitsubishi and failed. I got these old 4Meg SIMMS for free
which is why I'm using them.

I've written to the SIMM and filled it with the alphabet repeating over
and over. I've left the power on for over 24 hours and read back and
compared the data and there were no errors reported, so I guess the code
I am now using works.


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Best regards

Tony

mICros
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2002\05\03@031954 by Peter L. Peres

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Tony, try to change the refresh algorythm to 512 consecutive (is that your
page size)  normal reads. It should refresh on read.

Peter

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