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'[PIC]: Branch and I/O timing questions'
2003\03\12@054817 by shoppa_piclist

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I'm going to be doing some very precise timing on a 16F628, and have
a few questions which are the result of reading apparently contradictory
information in the Microchip data sheet:

1. The data sheet tells me that CALL, GOTO, and taken BTFSS and BTFSC's
take two instruction (8 clock) cycles, and that's great.  But it also
tells me that ADDWF only takes one cycle, yet a ADDWF PCL,F is
truly a branch so I'd naively expect it to take two, and the instruction
fetch diagrams lead me even further to suspect that it will take two.
What's the real story here?

2.  I'm also left confused about when different operations "hit" the
PORTA and PORTB pins.  Do MOVWF, BCF, and BSF all cause the output to
change at pretty much the same place, or does the simpler MOVWF somehow
"outrace" the others?  The documents are fairly clear about what happens
if you do a BCF immediately followed by a BSF (it won't work!) but I'm
still confused as to whether a BSF PORTA,0 followed by a CLRF PORTA,F
is a reliable way of making an output pulse on Port A's low bit that
stays high for exactly one instruction (4 clock cycles).

Tim.

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2003\03\12@060316 by

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It seem to remember seeing somewhere that *any*
instruction modifying PCL, takes 2 inst cycles.
That is, any instruction whos net result is that
the CPU can *not* execute the instruction in the
next higher address (that is already loaded into
the instruction pipeline/cache).

And I don't know what happens if you add 0 to PCL. That
isn't a "branch" realy.
It might invalidate the cache pipeline anyway, and then
just re-load the same instruction again (and taking an extra
instr cycle).

/Jan-Erik Söderholm.

.....shoppa_piclistKILLspamspam@spam@TRAILING-EDGE.COM wrote:

>The data sheet tells me that CALL, GOTO, and taken BTFSS and BTFSC's
>take two instruction (8 clock) cycles, and that's great.  But it also
>tells me that ADDWF only takes one cycle, yet a ADDWF PCL,F is
>truly a branch so I'd naively expect it to take two, and the instruction
>fetch diagrams lead me even further to suspect that it will take two.
>What's the real story here?

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2003\03\12@060319 by hael Rigby-Jones

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> -----Original Message-----
> From: .....shoppa_piclistKILLspamspam.....TRAILING-EDGE.COM
> [SMTP:EraseMEshoppa_piclistspam_OUTspamTakeThisOuTTRAILING-EDGE.COM]
> Sent: Wednesday, March 12, 2003 10:38 AM
> To:   PICLISTspamspam_OUTMITVMA.MIT.EDU
> Subject:      [PIC]: Branch and I/O timing questions
>
> I'm going to be doing some very precise timing on a 16F628, and have
> a few questions which are the result of reading apparently contradictory
> information in the Microchip data sheet:
>
> 1. The data sheet tells me that CALL, GOTO, and taken BTFSS and BTFSC's
> take two instruction (8 clock) cycles, and that's great.  But it also
> tells me that ADDWF only takes one cycle, yet a ADDWF PCL,F is
> truly a branch so I'd naively expect it to take two, and the instruction
> fetch diagrams lead me even further to suspect that it will take two.
> What's the real story here?
>
Any writes to PCL will take 2 instructions, so your suspicions are correct.
There is a note to theis effect at the bottom of the instruction set summary
in the datasheets.

> 2.  I'm also left confused about when different operations "hit" the
> PORTA and PORTB pins.  Do MOVWF, BCF, and BSF all cause the output to
> change at pretty much the same place, or does the simpler MOVWF somehow
> "outrace" the others?  The documents are fairly clear about what happens
> if you do a BCF immediately followed by a BSF (it won't work!) but I'm
> still confused as to whether a BSF PORTA,0 followed by a CLRF PORTA,F
> is a reliable way of making an output pulse on Port A's low bit that
> stays high for exactly one instruction (4 clock cycles).
>
CLRF is not a Read-Modify-Write operation, so following a BSF immediately by
a CLRF is perfectly valid.

Regards

Mike





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2003\03\12@062838 by shoppa_piclist

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>Any writes to PCL will take 2 instructions, so your suspicions are correct.
>There is a note to theis effect at the bottom of the instruction set summary
>in the datasheets.

That's what confused me; Note 3 at the bottom of Table 15-2 seems only
to apply to DECFSZ, INCFSZ, BTFSC, and BTFSS according to the nomenclature.
I suppose that this is a typo, or that I was taking the table too
literally.  Thanks for confirming that my not-so-literal interpretation
was correct :-)

>CLRF is not a Read-Modify-Write operation, so following a BSF immediately by
>a CLRF is perfectly valid.

Section 5.3.1, where they talk about Read-Modify-Write operations on ports,
leads me to think that maybe timing for a BSF/BCF is different than for
a simple CLRF.  But I think that Figure 5-16 might be saying that the
actual write to a port is always delayed for one-and-a-quarter instructions
(even though it is only showing a MOVWF PORTB and some NOP's, they don't
actually illustrate how a BSF or BCF might be different.)

Tim

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2003\03\12@063725 by

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----------
>From: Michael Rigby-Jones <spamBeGoneMichael.Rigby-JonesspamBeGonespamBOOKHAM.COM>
>To: TakeThisOuTPICLISTEraseMEspamspam_OUTMITVMA.MIT.EDU
>Subject: Re: [PIC]: Branch and I/O timing questions
>> 2.  I'm also left confused about when different operations "hit" the
>> PORTA and PORTB pins.  Do MOVWF, BCF, and BSF all cause the output to
>> change at pretty much the same place, or does the simpler MOVWF somehow
>> "outrace" the others?  The documents are fairly clear about what happens
>> if you do a BCF immediately followed by a BSF (it won't work!) but I'm
>> still confused as to whether a BSF PORTA,0 followed by a CLRF PORTA,F
>> is a reliable way of making an output pulse on Port A's low bit that
>> stays high for exactly one instruction (4 clock cycles).
>>
> CLRF is not a Read-Modify-Write operation, so following a BSF immediately by
> a CLRF is perfectly valid.
But don't forget that one of the reasons that Read-Modify-Write can lead to
unintended behaviour is because of the capacitance of the pins and the
external load. I don't know how precise your timing requirements are, but
the length of time for which the output is at logic level 1 will be affected
by this capacitance, and may not be exactly 4 clock cycles.

Jonny

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2003\03\12@063932 by Alan B. Pearce

face picon face
> 2.  I'm also left confused about when different operations "hit" the
> PORTA and PORTB pins.  Do MOVWF, BCF, and BSF all cause the output to
> change at pretty much the same place, or does the simpler MOVWF somehow
> "outrace" the others?  The documents are fairly clear about what happens
> if you do a BCF immediately followed by a BSF (it won't work!) but I'm
> still confused as to whether a BSF PORTA,0 followed by a CLRF PORTA,F
> is a reliable way of making an output pulse on Port A's low bit that
> stays high for exactly one instruction (4 clock cycles).

Others have already said about modifying PCL, so I'll stick to this.

The output bit of the port is modified on the 3rd or 4th clock cycle of the
instruction cycle (cannot remember which), but when doing a R/M/W which any
instruction apart from a Movwf portx instruction is (I'll ignore the fact
that this is also RMW, with the read thrown away for this discussion) reads
the port on the 2nd (IIRC) cycle of the clock. This is part of the reason
that the instruction cycle is 4 oscillator clocks long.

This means that if you have two RMW instructions as consecutive
instructions, then you have two oscillator cycles for the port to stabilise
before the next read comes along. If a bit has changed state then it may not
have reached the new level before the read of the second instruction takes
place, giving an erroneous read, which gets written back as an erroneous
value on the second write. Two consecutive instructions like this may work,
it is dependant on the port loading, so saying it won't work is not totally
correct. For this reason it is generally recommended that another
instruction be inserted between the two port operations, a NOP if there is
nothing else useful to do. This then gives 6 oscillator clocks for the port
bit to stabilise before being read, which gives considerably more time for
it to stabilise to a new level.

It is still possible to have erroneous values read back if the load on the
port is such that the voltage is held at a level which does not reach the
appropriate input threshold voltage. This normally happens when something
like an LED or transistor is driven in a dubious manner, such as not having
suitable resistors, and excessively loads the port. This can also create
problems, and the fix is to use a shadow register so the port is only ever
written to, or preferably to fit appropriate resistors to allow the port to
achieve proper levels.

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2003\03\12@084927 by Bob Ammerman

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> 1. The data sheet tells me that CALL, GOTO, and taken BTFSS and BTFSC's
> take two instruction (8 clock) cycles, and that's great.  But it also
> tells me that ADDWF only takes one cycle, yet a ADDWF PCL,F is
> truly a branch so I'd naively expect it to take two, and the instruction
> fetch diagrams lead me even further to suspect that it will take two.
> What's the real story here?

Any instruction writing to PCL (including ADDWF PCL,F) is two cycles.

> 2.  I'm also left confused about when different operations "hit" the
> PORTA and PORTB pins.  Do MOVWF, BCF, and BSF all cause the output to
> change at pretty much the same place, or does the simpler MOVWF somehow
> "outrace" the others?  The documents are fairly clear about what happens
> if you do a BCF immediately followed by a BSF (it won't work!) but I'm
> still confused as to whether a BSF PORTA,0 followed by a CLRF PORTA,F
> is a reliable way of making an output pulse on Port A's low bit that
> stays high for exactly one instruction (4 clock cycles).

Changes all hit the port at the same point in the instruction cycle,
regardless of the instruction.

Depending on capacitance on the pin BCF followed by BSF will work.

Alternatively:

   movf    PORTA,W        ; remember PORTA
   bcf       PORTA,x          ; turn off pin
   movwf  PORTA            ; turn it back on


Bob Ammerman
RAm Systems

> Tim.
>
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2003\03\12@085550 by

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Even if the write do not *modify* the value of PCL ?
(Such as ADDWF PCL,F when W = 0)

In theory, the PIC should be able to use the already loaded
instruction in the pipeline, not ?

Jan-Erik Söderholm.



Bob Ammerman wrote:
>Any instruction writing to PCL (including ADDWF PCL,F) is two cycles.

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2003\03\12@093530 by Olin Lathrop

face picon face
> 1. The data sheet tells me that CALL, GOTO, and taken BTFSS and BTFSC's
> take two instruction (8 clock) cycles, and that's great.  But it also
> tells me that ADDWF only takes one cycle, yet a ADDWF PCL,F is
> truly a branch so I'd naively expect it to take two, and the instruction
> fetch diagrams lead me even further to suspect that it will take two.
> What's the real story here?

ADDWF normally takes one cycle.  However, any instruction that modifies
the PC takes two cycles.  They just didn't point out that ADDWF to PCL
will therefore take two cycles.  So will SUBWF PCL, IORWF PCL, etc.

The simulator can be very useful in counting cycles, particularly when the
"stopwatch window" is used.

> 2.  I'm also left confused about when different operations "hit" the
> PORTA and PORTB pins.  Do MOVWF, BCF, and BSF all cause the output to
> change at pretty much the same place, or does the simpler MOVWF somehow
> "outrace" the others?

All writes to port registers happen on the same Q cycle regardless of
which instruction is used (at least so I recall).

> but I'm
> still confused as to whether a BSF PORTA,0 followed by a CLRF PORTA,F
> is a reliable way of making an output pulse on Port A's low bit that
> stays high for exactly one instruction (4 clock cycles).

Huh?  It will go low due to the BSF, then all the other port A bits will
also go low one instruction later.


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Embed Inc, embedded system specialists in Littleton Massachusetts
(978) 742-9014, http://www.embedinc.com

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2003\03\12@101249 by Olin Lathrop

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> Even if the write do not *modify* the value of PCL ?
> (Such as ADDWF PCL,F when W = 0)
>
> In theory, the PIC should be able to use the already loaded
> instruction in the pipeline, not ?

In theory, but I would be very surprised if the PIC included circuitry to
detect and handle this special case.


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Embed Inc, embedded system specialists in Littleton Massachusetts
(978) 742-9014, http://www.embedinc.com

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2003\03\12@101528 by Olin Lathrop

face picon face
>> but I'm
>> still confused as to whether a BSF PORTA,0 followed by a CLRF PORTA,F
>> is a reliable way of making an output pulse on Port A's low bit that
>> stays high for exactly one instruction (4 clock cycles).
>
> Huh?  It will go low due to the BSF, then all the other port A bits will
> also go low one instruction later.

Sorry, I somehow read the BSF as BCF.  Yes, this should produce a one
cycle high pulse, assuming the pin was low before the BSF.


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(978) 742-9014, http://www.embedinc.com

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2003\03\12@101530 by Wouter van Ooijen
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> And I don't know what happens if you add 0 to PCL. That
> isn't a "branch" realy.
> It might invalidate the cache pipeline anyway, and then
> just re-load the same instruction again (and taking an extra
> instr cycle).

it does.

Wouter van Ooijen

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2003\03\12@104636 by hael Rigby-Jones

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> > but I'm
> > still confused as to whether a BSF PORTA,0 followed by a CLRF PORTA,F
> > is a reliable way of making an output pulse on Port A's low bit that
> > stays high for exactly one instruction (4 clock cycles).
>
> {Original Message removed}

2003\03\13@081617 by Bob Ammerman

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ADDWF PCL,F does take two cycles, even if W is zero.

It would require special hardware on the chip to detect the addition of zero
to suppress the extra cycle. (And then what about IORWF PCL,F with W=0, or
ANDWF PCL,F with W=0xFF, etc).

It would also mess up timing calculations that depended on various code
paths taking the same amount of time.

While we are on this thought.... think about the instruction:

       DECF    PCL,F

Bob Ammerman
RAm Systems

{Original Message removed}

2003\03\13@100353 by Scott Dattalo

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On Wed, 12 Mar 2003, Bob Ammerman wrote:

> ADDWF PCL,F does take two cycles, even if W is zero.
>
> It would require special hardware on the chip to detect the addition of zero
> to suppress the extra cycle. (And then what about IORWF PCL,F with W=0, or
> ANDWF PCL,F with W=0xFF, etc).
>
> It would also mess up timing calculations that depended on various code
> paths taking the same amount of time.
>
> While we are on this thought.... think about the instruction:
>
>         DECF    PCL,F

If the lower 8-bits of the address of this instruction are not zero then
this is a goto $ (or a bra $ on the 18F). If they are zero then this is a
goto $+0xff.

Has anyone ever heard of the skip and clear Z instruction? It works most
of the time! :)

Scott

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2003\03\13@163835 by Bob Ammerman

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> Has anyone ever heard of the skip and clear Z instruction? It works most
> of the time! :)
>
> Scott

INCF    PCL,F

Bob

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