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'[PIC]: And now for somehting different...the 18xx '
2000\06\29@094953 by o-8859-1?Q?K=FCbek_Tony?=

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Hi,
Slowly working my way into the pits of the Pic's and now the time
has come to struggle the 18xx beasts. I've read the datasheets
and the 'migration documents' and had a few "aha's" but i would
like to have some opinions of more efficient use of this series.
Anyone come up with clever ideas to implement the new features ?
Any findings/hints/etc someone would like to convey ?

BTW never used an PIC with HW multiplicator before so this is
my current starting point for my enlightment.

Also never used 'C' in a PIC project before as the snippets
I've seen were looking alot more like ASM than 'pure' C. An
if this is the case why bother ?. But regarding the 18xx series
, which are supposed to be C-enhanced ( more suitable for it anyway )
is it beneficial to start using C all togehter ?
( I know this has been disccused several times before, but I asking
in specific to the 18xx series ONLY ).

/Tony


Tony Kübek, Flintab AB            
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2000\06\29@102904 by Scott Dattalo

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On Thu, 29 Jun 2000, [Iso-8859-1] Kübek Tony wrote:

> Hi,
> Slowly working my way into the pits of the Pic's and now the time
> has come to struggle the 18xx beasts. I've read the datasheets
> and the 'migration documents' and had a few "aha's" but i would
> like to have some opinions of more efficient use of this series.
> Anyone come up with clever ideas to implement the new features ?
> Any findings/hints/etc someone would like to convey ?
>
> BTW never used an PIC with HW multiplicator before so this is
> my current starting point for my enlightment.
>
> Also never used 'C' in a PIC project before as the snippets
> I've seen were looking alot more like ASM than 'pure' C. An
> if this is the case why bother ?. But regarding the 18xx series
> , which are supposed to be C-enhanced ( more suitable for it anyway )
> is it beneficial to start using C all togehter ?
> ( I know this has been disccused several times before, but I asking
> in specific to the 18xx series ONLY ).

This is certainly an open-ended question!

There are many architectural changes that make the 18cxxx parts superior
devices. I think two stand out rather boldly. One is the enhancements for
indirect addressing. The 18cxxx has three indirect registers and 4-modes in
which they can operate (indirect access, pre-increment, post-increment,
post-decrement). Second are the enhancements for directly accessing programming
memory (actually this was in the 17cxx family).

Below are two versions of my sine routine. The first is written for the 14-bit
core the second for the 16-bit core (18cxxx). The latter is two-thirds smaller.

www.dattalo.com/technical/software/pic/picsine.html
http://www.dattalo.com/technical/software/pic/sine18.asm


Scott

2000\06\29@140036 by Thomas C. Sefranek

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Scott Dattalo wrote:

> There are many architectural changes that make the 18cxxx parts superior
> devices. I think two stand out rather boldly. One is the enhancements for
> indirect addressing. The 18cxxx has three indirect registers and 4-modes in
> which they can operate (indirect access, pre-increment, post-increment,
> post-decrement).

Yes, BUT it has no way of passing an argument to the FSRs, only absolutes are
allowed.
(LSFR)
[Atleast that's what I understand.]

> Second are the enhancements for directly accessing programming
> memory (actually this was in the 17cxx family).

Yes, BUT!!! the defaults are exactly WRONG, almost every second line of code must
include
",SFR" to tell the assembler you mean to use the Special Function Registers.
Boy!  Talk about a bad call!
If you do lots of internal memory operations in math then the defaults make sense,
but This is NOT a math engine, it's a I/O device, and access tot he SFRs should
have been
the default in the assembler.
[Atleast that's what I understand.]

>
>
> Below are two versions of my sine routine. The first is written for the 14-bit
> core the second for the 16-bit core (18cxxx). The latter is two-thirds smaller.
>
> www.dattalo.com/technical/software/pic/picsine.html
> http://www.dattalo.com/technical/software/pic/sine18.asm
>
> Scott

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2000\06\29@141116 by Harold M Hallikainen

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       I've moved two designs from the 16c74 to the 18c452 and am now working
on my third. I did it mostly to get more on-chip RAM, but the hardware
multiply allowed me to add features to one product (software multiply
would have slowed it down to a crawl). The several FSR's are nice (I
could always use more). The auto-increment/decrement is also useful. The
FSR's are now 12 bit, which is nice to easily reach all of RAM.
Something that caught me TWICE is that the FSRs are indeed only 12 bits
(not 16, even though they are fsrh and fsrl, which COULD be 16 bits). So
the fsr decrements from 0x0000 to 0x0fff. I was checking for 0xffff and
never finding it...
       The "access bank" is nice. If you put scratch ram between 0x00 and 0x7f,
you can get to it with no bank switching. Using the "access bank" you can
quickly get to this low RAM and the SFR's in high memory. There is a bank
select register that can be loaded with a literal without going thru w (I
use something like movlb high(TxBuf) ). NOTE that the default is to use
BANKED (using the BSR) instead of the access bank. If BSR is set to 0,
this is generally equivalent (though you can't get to the SFR's that
way...).
       Another nice thing is the RETFEI FAST instruction. This is a bit like
the shadow registers in the Z80. Going into an interrupt, W, STATUS, and
BSR are stored in shadow registers. RETFEI FAST restores these registers,
saving you from a save and restore context. HOWEVER, PCLATH is NOT
stored, so you'll generally need to do that.
       Another thing to watch out for is jump tables. On the 16c74, each
instruction (including goto) was one word. You could do a jump table like
this...

       movlw   high($)
       movwf   pcalth          ; Set pclath for table jump
       movf    state,0         ; get current state in w
       addwf   pcl,1           ; go into jump table
       goto    state0
       goto    state1
       goto    state2

       The shortest branch instruction on the 18c452 is the BRAnch instruction,
which is two bytes. So, you have to multiply the state by 2 prior to
doing the addwf pcl.

       movlw   high($)
       movwf   pcalth,0        ; Set pclath (using access bank) for table jump
       rlncf   state,0,0       ; get current state times 2 in w (assuming state is in
access bank)
       addwf   pcl,1,0         ; go into jump table (pcl is in access bank)
       bra     state0
       bra     state1
       bra     state2

       Finally, watch out for pclatu. This is loaded into the highest 4 bits of
the PC on some instructions (like addwf pcl,1,0). Pclatu is cleared on
reset, so this should not be a problem. An early version of the MPLAB ICE
changed PCLATU and PCLATH during a goto in the reset vector location,
messing up all jump tables from there on out (the emulator read
nonexistant memory). That's fixed now!
       There's lots of other stuff in the 18c452 I haven't dealt with yet,
since I'm mostly migrating stuff to it without major code changes. The 32
word stack looks nice. You can also put user data on the stack, which
should be nice for local variables in both assembly and higher level
languages (though I have not used it for that yet... Keeps every routine
from having their own temp and counter variables... just reuse stuff on
the stack!).

Harold



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2000\06\29@144021 by Scott Dattalo

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On Thu, 29 Jun 2000, Thomas C. Sefranek wrote:

> Scott Dattalo wrote:
>
> > There are many architectural changes that make the 18cxxx parts superior
> > devices. I think two stand out rather boldly. One is the enhancements for
> > indirect addressing. The 18cxxx has three indirect registers and 4-modes in
> > which they can operate (indirect access, pre-increment, post-increment,
> > post-decrement).
>
> Yes, BUT it has no way of passing an argument to the FSRs, only absolutes are
> allowed.
> (LSFR)
> [Atleast that's what I understand.]

I don't follow you here. Could you explain what you mean?

{Quote hidden}

Basically, you object to there being a third operand to the assembly
instruction? That doesn't bother me personally. It's only needed if you wish to
directly access the SFRs while the bank register is pointing to a bank other
than the SFR bank. In fact, I'd go so far to say it's a feature to have direct
access to the SFRs regardless of the currently addressed bank. One could
certainly define a new set of macros for SFR accesses... but that'd be a pain.

I suppose one could change the assembler such that accesses to the last bank
(the one containing the SFRs) could automagically generate the proper value for
the 'access' bit in the instruction. That is, assuming one had access to the
code. Maybe that feature will appear in gpasm one day...

Scott

2000\06\29@160943 by Darrel Johansen

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Thomas C. Sefranek wrote:

>Yes, BUT!!! the defaults are exactly WRONG, almost every second line of
code must
>include ",SFR" to tell the assembler you mean to use the Special Function
Registers.
>Boy!  Talk about a bad call!
>If you do lots of internal memory operations in math then the defaults
make sense,
>but This is NOT a math engine, it's a I/O device, and access tot he SFRs
should
>have been the default in the assembler.
>[Atleast that's what I understand.]

Good discussion on the 18Cxxx, everybody.

One point of clarification:
I don't know what assembler Mr. Sefranek is talking about, but MPASM will
AUTOMATICALLY determine whether or not the bank bit has to be used in the
processor.  It does this by knowing where the access "split" is (0x7f and
0xF80 on these first few chips).  If you define a variable at address
0x60=temp0, 0x100=temp1, and want to access a special function register,
you can have your BSR pointing to bank 1 (with BANKSEL 0x100), then write
your code without worrying about the access register bit:

  BCF    INTCON2,RBIP
  MOVLW  0x27
  MOVWF  temp1
  CLRF   temp0

If you look at the instructions generated by MPASM, you'll see that the
bank bit is properly set for all accesses, and you probably don't ever have
to worry about the bank bit (though you'd better be careful of the BSR if
you are using variables in other banks).  In fact, even the built in
assembler of MPLAB (in the Modify Dialog) is smart this way!

There is no default, but you can force it to generate wrong code with:

  BCF    INTCON2,RBIP,1
or
  BCF    INTCON2,RBIP,BANKED
or
  MOVWF  temp1,ACCESS

Harold has some good points, and probably as much or more practical
experience with the chip than anyone.  Thanks for helping us get the
glitches out of the emulator, Harold!

Darrel Johansen
Microchip Technology Inc.

2000\06\29@162305 by Fansler, David

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Is ICD available (MicroChip or other) available for the 18xx series?  I love
my ClearMathias emulator and realize it will never support the 18xx series,
so ICD would seem the next logical (read inexpensive) way to debug.
Thanks,
David V. Fansler
Network Administrator
TriPath Imaging, Inc. (Formerly AutoCyte, Inc)
336-222-9707 Ext. 261
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Updated June 1, 2000
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               {Original Message removed}

2000\06\29@163046 by Bob Ammerman

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See comments marked **** below. Based on writing an rather large program in
assembly on an 18Cxx2

Bob Ammerman
RAm Systems
(high performance, high function, low-level software)

**** The 18C instruction set is very nice. The memory map makes more sense
than any other PIC to date. And of course 10MIPS performance is nothing to
complain about either.

**** You do have to worry about the 2 word instructions tho'. Those extra
words of memory and cycles can sneak up on you.

**** You lose the 1 word, 1 cycle MOVFP and MOVPF instructions.

**** There are many neat things that can be done with the accessible
'top-of-stack' registers.

{Original Message removed}

2000\06\29@163301 by Harold M Hallikainen

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On Thu, 29 Jun 2000 13:13:34 -0700 Darrel Johansen
<EraseMEDarrel.Johansenspam_OUTspamTakeThisOuTMICROCHIP.COM> writes:
>
> Harold has some good points, and probably as much or more practical
> experience with the chip than anyone.  Thanks for helping us get the
> glitches out of the emulator, Harold!
>
> Darrel Johansen
> Microchip Technology Inc.

       Thanks for all the support! It was fun trying to figure out if it was
something I was doing wrong or something wrong in the emulator. I'm
working with it right now and it does exactly what the code tells it to
do!

Harold



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2000\06\29@171838 by Darrel Johansen

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>Is ICD available (MicroChip or other) available for the 18xx series?  I
love
>my ClearMathias emulator and realize it will never support the 18xx
series,
>so ICD would seem the next logical (read inexpensive) way to debug.

I can't comment specifically on unreleased parts or products.  The
Development Systems group will probably support most flash products with
ICD type systems.

Darrel Johansen

2000\06\29@185244 by Thomas C. Sefranek

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Bob Ammerman wrote:

{Quote hidden}

Thanks!  I understand now.

{Quote hidden}

I admire your style, but I began to HATE adding the option to each command that
needed it.
The BEST news is:  I don't have to do it!  Thanks, the assembler does the right
thing.

Now IF only they could deliver my PCM card for the 18C452 for the ICE-2000.
(I seem to recall something about mid June...)

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2000\06\29@185258 by Thomas C. Sefranek

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Darrel Johansen wrote:

A big THANK YOU Darrel!

{Quote hidden}

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2000\06\30@052908 by o-8859-1?Q?K=FCbek_Tony?=

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Hi,
Thanks to all who responded ! it really hightens my belives in the list
:-)
Anyway here are some minor replies:

Scott Dattalo wrote:

>This is certainly an open-ended question!

You think ? .. :-) , yes I know but at this time I dont
have any specific questions as I'm just starting to mentally
adjust to the new features/quirks/etc. In time though I'll
probably have some more 'down to the metal' questions.

Bob Ammerman wrote:

>**** You do have to worry about the 2 word instructions tho'. Those
extra
>words of memory and cycles can sneak up on you.

How so ? you mean that it 'eats code space' or cycles ? or when doing
table jumps ?

>**** You lose the 1 word, 1 cycle MOVFP and MOVPF instructions.

Stubmled first, ( I've never heard of these instr. ) but then I realised
that there are 'other' PIC's which I havent 'played' with yet.
So I'm guessing these are from the 17xx series correct ?

>**** There are many neat things that can be done with the accessible
>'top-of-stack' registers.

Such as ?

>**** Not any big deal at all! Actually, my coding standard requires
>explicitly stating every option on every instruction. Helps preempt the
bug
>where you forget to specify what you want!

My way of coding/thinking ! ( even so I ocasionally misstype the ,W or
,F ;-) )

Harold Hallikainen wrote:

>I've moved two designs from the 16c74 to the 18c452 and am now working
>on my third. I did it mostly to get more on-chip RAM, but the hardware

Likewise and to get rid of the bank switching ( which is evil...) .

>use something like movlb high(TxBuf) ). NOTE that the default is to use
>BANKED (using the BSR) instead of the access bank. If BSR is set to 0,
>this is generally equivalent (though you can't get to the SFR's that
>way...).

Interesting, I need to read a bit more of what You mean by the BANKED
statement, seem that I've missed something going through the manuals.

>Finally, watch out for pclatu. This is loaded into the highest 4 bits
of
>the PC on some instructions (like addwf pcl,1,0). Pclatu is cleared on

Is this the same as the 'lower' pic's PCLATH ? i.e. if you dont clear it
the next goto could be fun :-)

And thanks to Darrel Johansen, nice to see that Microchip is sometimes
listening.

/Tony




Tony Kübek, Flintab AB            
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2000\06\30@092017 by Bob Ammerman

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See my notes marked !!!! below

Bob Ammerman
RAm Systems
(high performance, high function, low-level software)

{Original Message removed}

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