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'[PIC]: 18fxx2 Examples and ISR Question'
2002\12\10@124344 by Josh Koffman

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face
Ok, now I'm really about to start this project. I have been reading the
data sheets quite a bit, and I think I know basically what I'm doing.
However, if anyone has any snippets of code, basically showing proper
ways to do initializations, and how to handle interrupts, it would be
appreciated. I checked out http://www.picbook.com but unfortunately they
only use MASM for one of the examples. Any pointers would be
appreciated.

Also, I have a couple of questions about ISRs. I used to have this
straight in my mind, but I've confused myself too much by thinking about
it, and I can't figure it out now. On the 16F series, if I'm in the ISR,
GIE is cleared. If I receive an interrupt before I RETFIE (and thus
reset the GIE) it will get lost unless I check for it in software before
I issue the RETFIE right?

What about 18F series? I am super confused, because of the whole high
and low priority interrupt possibility.

Any guidance would be appreciated :)

Thanks,

Josh
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2002\12\10@133656 by Olin Lathrop

face picon face
> On the 16F series, if I'm in the ISR,
> GIE is cleared. If I receive an interrupt before I RETFIE (and thus
> reset the GIE) it will get lost unless I check for it in software before
> I issue the RETFIE right?

No.  The interrupt condition will set a flag bit, so the condition
persists until it is explicitly cleared.  Some flag bits are cleared by
other actions (like reading RCREG to clear the UART receive condition),
but in all cases that I can think of right now all flags are cleared by
deliberate action.

If an interrupt condition occurs during an interrupt and that condition is
not dealt with in the existing interrupt, then a new interrupt will occur
immediately after the RETFIE.  I usually design my interrupt routines to
only handle one condition at a time.  If two conditions happen to occur
simultaneously, then I'll get two back to back interrupts.  No big deal.


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2002\12\10@141939 by Harold Hallikainen

picon face
I really don't think you'll lose any interrupts. On both the 16 and 18 (I believe), having GIE clear merely prevents the processor from responding to the interrupt. As soon as GIE is set, the processor responds if appropriate IE and IF bits are set. I've gotten into situations where I forgot to clear the IF bit in an ISR. My non-interrupt code never ran (or maybe ran one instruction, then interrupt ran, then another instruction of non-ISR code).

As far as I know, the 18fxx2 is the same processor as the other 18c or 18f parts. If you run non-prioritized interrupts, a lot of code moves directly from 16 to 18. The 18 has "retfie 1", which restores w, status, and bsr from shadow registers so you don't have to do a save/restore context like on the 16. Otherwise, not a whole lot different. There are several new instructions in the 18, but almost all the old 16 instructions behave exactly the same on the 18. There are a few differences in how flags are affected, so watch out for that.

I've migrated several products from 16 to 18 processors with no trouble. I'm now working on a project for the 18f6720 in C. So far, I have not had to use interrupts on that one. All the other projects have interrupts.

Harold

---------- Josh Koffman <spam_OUTlistsjoshTakeThisOuTspam3MTMP.COM> writes:

Also, I have a couple of questions about ISRs. I used to have this
straight in my mind, but I've confused myself too much by thinking about
it, and I can't figure it out now. On the 16F series, if I'm in the ISR,
GIE is cleared. If I receive an interrupt before I RETFIE (and thus
reset the GIE) it will get lost unless I check for it in software before
I issue the RETFIE right?

What about 18F series? I am super confused, because of the whole high
and low priority interrupt possibility.

Any guidance would be appreciated :)

Thanks,

Josh
--
A common mistake that people make when trying to design something
completely foolproof is to underestimate the ingenuity of complete
fools.
       -Douglas Adams

--
http://www.piclist.com hint: The PICList is archived three different
ways.  See http://www.piclist.com/#archives for details.





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