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'[PIC]: 18Fxx2 help'
2002\11\30@003519 by Josh Koffman

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Hi all. I'm about to start coding for the 18Fxx2 family, specifically
the 18f252 and 18f452. Does anyone have any examples of well written
code for these chips? I am particularly confused by the banking
differences. My code was mainly pretty small on the 16f series, so I
never ran into program page banking, and RAM banking was pretty easy.
However, it seems to be much more complicated on the 18F series, and I'm
pretty confused. Help!

Thanks,

Josh
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2002\11\30@015628 by cdb

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If you leave the BSR register at 0x00 (the default), and your
variables are at addresses 0x000 - 0x07F that is 128 variables you
will not have to use banking. For  complete 256 variables the BSr can
be set to 0x01 and address 0x100-0x1FFF

Some 18F specific examples are available at http://www.picbook.com.

Colin
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2002\11\30@092427 by Bob Ammerman

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> If you leave the BSR register at 0x00 (the default), and your
> variables are at addresses 0x000 - 0x07F that is 128 variables you
> will not have to use banking. For  complete 256 variables the BSr can
> be set to 0x01 and address 0x100-0x1FFF

Better yet:

The 18Fxx2 series provides an "access" page which provides continuous access
to the first 128 ram locations and all the FSRs without having to adjust any
banking register.

If you then set the BSR to 1 you will have an additional directly
addressable RAM locations (0x100 to 0x1FF).

To access locations 0x80 through 0xFF and 0x200 thru 0x5FF you can use the
FSR's (which are now 12-bit registers) to point to the location needed.

This works out quite well for many programs because 384 bytes is plenty for
miscellaneous variables and the remaining memory is easily used for buffers
and arrays.

Bob Ammerman
RAm Systems

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2002\11\30@094343 by Olin Lathrop

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> Hi all. I'm about to start coding for the 18Fxx2 family, specifically
> the 18f252 and 18f452. Does anyone have any examples of well written
> code for these chips? I am particularly confused by the banking
> differences. My code was mainly pretty small on the 16f series, so I
> never ran into program page banking, and RAM banking was pretty easy.
> However, it seems to be much more complicated on the 18F series, and I'm
> pretty confused. Help!

It's actually easier on the PIC18 compared to the PIC16.  The GOTO and
CALL instructions contain the full 20 address bits to go to any
instruction in program memory.  PCLATH and PCLATU therefore don't effect
these instructions, and there are no issues of "paging".  You still have
to be aware of PCLATH and PLATU when directly modifying PCL.


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2002\11\30@120720 by Josh Koffman

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Arg...if only the website hadn't exceeded its bandwidth. On the upside,
the end of the month is near heh. Thank you all for your responses...one
thing I am a little hazy on is still the access bank. I know the first
128 bytes are GPR, and the second 128 are SFR. Does this mean that I can
set the SFRs directly, without having to bank switch, as in the 16f?
Also, what happens when I set the BSR to 0x01? Are there 128 new SFRs,
or do they map to the same SFRs as BSR=0x00? I just am trying to get a
simple blinky LED program going.

Thanks,

Josh
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cdb wrote:
> If you leave the BSR register at 0x00 (the default), and your
> variables are at addresses 0x000 - 0x07F that is 128 variables you
> will not have to use banking. For  complete 256 variables the BSr can
> be set to 0x01 and address 0x100-0x1FFF
>
> Some 18F specific examples are available at http://www.picbook.com.

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2002\11\30@160525 by Olin Lathrop

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> one
> thing I am a little hazy on is still the access bank. I know the first
> 128 bytes are GPR, and the second 128 are SFR. Does this mean that I can
> set the SFRs directly, without having to bank switch,

Yes.  The access bank can always be directly accessed without regard to
BSR.

> as in the 16f?

Huh?  The PIC16 has no "access bank" mechanism.

> Also, what happens when I set the BSR to 0x01?

That's what I recommend you do until you know enough and have an unusual
situation where that's not good enough.  BSR set to 1 selects 100h - 1FFh
as the 8 bit data address space that can be accessed directly.  The access
bank and registers accessed thru BSR are essentially two independent
address spaces.  The access bank always allows direct access to 0 - 7Fh
and F80h - FFFh.  With BSR = 1 you can also access 100h - 1FFh directly in
any instruction without needing to mess with bank switching.


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'[PIC]: 18Fxx2 help'
2002\12\01@010626 by Josh Koffman
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Ok, I reread my original post, and it seems that lack of sleep was
making it hard for me to articulate my thoughts last night. What I meant
about the 16f series and access bank was that as long as a SFR is mapped
to the access bank, I can use it regardless of the value of the BSR.
And, thus I can set TRIS values without having to bank select, which is
what I would have to do in a 16f chip. Correct?

Also, when defining data RAM (equ or cblock), how do I define the
registers in BSR=0x01? Do I have to offset them and give them a higher
value (.128+), or do they map to .1+?

Thanks,
Josh
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Olin Lathrop wrote:
{Quote hidden}

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2002\12\01@091440 by Olin Lathrop

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> What I meant
> about the 16f series and access bank was that as long as a SFR is mapped
> to the access bank, I can use it regardless of the value of the BSR.

The PIC16 has no access bank.  On the PIC18, all special function registers
are accessible via the access bank.  The address range F80h - FFFh is
specifically reserved for SFRs, which is also the second half of the access
bank.

> And, thus I can set TRIS values without having to bank select, which is
> what I would have to do in a 16f chip. Correct?

Yes.  Any SFR access on a PIC18 can be done via the access bank.

> Also, when defining data RAM (equ or cblock), how do I define the
> registers in BSR=0x01? Do I have to offset them and give them a higher
> value (.128+), or do they map to .1+?

You don't define registers as belonging to a particular BSR setting, but you
can define them in the address range that can be directly accessed by a
particular BSR setting.  If you want to be able to access a register with
BSR=1, then you need to make sure its address is 100h - 1FFh.


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2002\12\01@192658 by Bob Ammerman

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To understand addressing in the 18F you need to know what an address looks
like in the instruction itself.

Unlike the 16F, where addresses were stored as only 7 bits in the
instruction; in the 18F addresses are stored as 2 separate fields: a 1-bit
field call the "ram access bank" and  an 8-bit field called the "file
register address".

These two fields are combined as follows to determine the effective address
of the file register to be used:

if the "ram access bank" bit is a 1 then

   the effective address is BSR:"file register address".
   In other words, the effective address is constructed
   using BSR to provide the high order 4 bits and
   8 bits from the instruction to provide the low order
   8 bits. This allows you to access 256 bytes in the
   bank pointed to by BSR.

else if the high bit of the "file register address" is a 0 then

   the effective address is just the file register address. This
   allows access to the first 128 bytes of memory regardless
   of the setting of BSR.

else (the high bit of the "file register address is 1) then

   the effective address is X'F':"file register address. This
   will result in addresses in the range X'F80' through
   X'FFF', which are the SFRs.

end if

> Also, when defining data RAM (equ or cblock), how do I define the
> registers in BSR=0x01? Do I have to offset them and give them a higher
> value (.128+), or do they map to .1+?

The assembler will by default access any register in the ranges
X'000'..X'7Fh' or X'F80' using the "access bank". Otherwise, the assembler
will assume that the specified register is in the bank currently pointed to
by the BSR.

So, that means that your variables in bank 1 should be declared as being at
addresses X'100' through X'1FF'.

Bob Ammerman
RAm Systems

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