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'[PIC]: 18 series vs. 16 series'
2002\12\04@215950 by Dave Muhlert

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Thanks a lot for your input.  Since you recommended using the 16f877, I may
as well ask the question I've been thinking of for a while.  I am very new
to PIC programming, and in fact the only one I have any experience with is
the 18f452.
       I've heard from my instructor numerous times that a number of things are
much more complicated to code for the 16 series PICs than for the 18 series.
How much does the code generally change from one model to the next?  I just
want to know how much I should expect to re-learn if/when I switch PICs,
which I'm sure will happen if I end up designing any real circuits.

-Dave Muhlert

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2002\12\05@074411 by Olin Lathrop

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>         I've heard from my instructor numerous times that a number of
things are
> much more complicated to code for the 16 series PICs than for the 18
series.
> How much does the code generally change from one model to the next?  I
just
> want to know how much I should expect to re-learn if/when I switch PICs,
> which I'm sure will happen if I end up designing any real circuits.

The 16 series has a 14 bit instruction word, whereas the 18 has a 16 bit
instruction word.  The extra bits, among other things, simplify the data
addressing model.  Some key instructions that address program memory, like
GOTO and CALL, use 32 bits.  This allows them to directly address any
instruction in the 2Mb address space, which mostly eliminates program
memory paging concerns.  The 18 series is newer, faster, and has a
somewhat richer base instruction set, including an 8 x 8 bit mulitplier.
Otherwise, the instructions are basically similar, often identical in
operation.  If you looked at the instruction set of a 16F877 it would look
familiar, but you'd probably get caught by bank and page switching at
first.

Since the 18 series is the current "new" family, this is where new
features will be introduced.  They are also fabbed with the latest
process, often making them cheaper than comparable 16 series PICs at high
volumes.

If you are already familiar with the 18 series, I would stick with it
unless you are designing a high volume product and you can find just the
right 16 or 12 family part to do the job at a lower price.  The 18 series
does not have the low end that the 16 series does, and it has nothing
comparable to the 12 series.


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2002\12\05@162151 by Harold Hallikainen

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---------- Dave Muhlert <spam_OUTdavemTakeThisOuTspamDRLASER.ORG> writes:


       I've heard from my instructor numerous times that a number of things are
much more complicated to code for the 16 series PICs than for the 18 series.
How much does the code generally change from one model to the next?  I just
want to know how much I should expect to re-learn if/when I switch PICs,
which I'm sure will happen if I end up designing any real circuits.


-------------------------

Off the top of my head, the main differences are:

The 18 series has hardware multiply, table read from ROM (instead of requiring RETLW), several FSR/INDF registers, auto increment/decrement on FSR/INDFs. wider FSRs making it easier to get anywhere in RAM, more RAM, faster processor (I'm running an 18F6720 at 40 MHz using a 10MHz resonator and the 4xPLL in the PIC), easier to access I/O using the "access bank".

Most of my products started with 16 series chips with code in assembly. A couple had to move to 18 to get more RAM, more ROM, or more speed. Other stuff has stayed with 16. On new products, I try to anticipate RAM/ROM  and I/O requirements and go with the cheapest chip that will do the job. If there's a LOT of multiplication, I move to something with hardware multiply. If not, I stay with software unless something else moves me to 18.

The two projects I'm working on right now have the following.

One uses the 18f6720 with code in C.

The other uses a 16lf627 and 16LF870.

Harold





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2002\12\06@080622 by Michael Rigby-Jones

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> -----Original Message-----
> From: Harold Hallikainen [SMTP:.....haroldhallikainenKILLspamspam@spam@JUNO.COM]
> Sent: Thursday, December 05, 2002 9:20 PM
> To:   PICLISTspamKILLspammitvma.mit.edu
> Subject:      Re: [PIC]: 18 series vs. 16 series
>
>  (I'm running an 18F6720 at 40 MHz using a 10MHz resonator and the 4xPLL
> in the PIC), easier to access I/O using the "access bank".
>
Are you aware that these parts are no longer rated to 40MHz?

http://www.microchip.com/download/lit/suppdoc/errata/80129b.pdf

Mike

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2002\12\06@084916 by Olin Lathrop

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> The 18 series has hardware multiply, table read from ROM (instead of
requiring RETLW),

Most (all ?) of the 16F parts can do this too.


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2002\12\06@103520 by Michael Rigby-Jones

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> -----Original Message-----
> From: Olin Lathrop [SMTP:olin_piclistspamspam_OUTEMBEDINC.COM]
> Sent: Friday, December 06, 2002 12:37 PM
> To:   @spam@PICLISTKILLspamspammitvma.mit.edu
> Subject:      Re: [PIC]: 18 series vs. 16 series
>
> > The 18 series has hardware multiply, table read from ROM (instead of
> requiring RETLW),
>
> Most (all ?) of the 16F parts can do this too.
>
The larger parts have the ability to read from program memory e.g. 16F87x.
16F7x but the smaller types such as 16F8x, 16F62x do not.  AFAIK none of the
14 bit cores has a hardware multiplier.

Mike

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2002\12\06@103918 by Peter McNulty

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The hardware multiply isn't very helpful if you want to do more than 8bit
multiplications, as it requires that you write everything the standard way
instead of utilising the multiply function of the chip.

-Peter
----- Original Message -----
From: "Michael Rigby-Jones" <RemoveMEmrjonesTakeThisOuTspamBOOKHAM.COM>
To: <spamBeGonePICLISTspamBeGonespamMITVMA.MIT.EDU>
Sent: Friday, December 06, 2002 11:33 PM
Subject: Re: [PIC]: 18 series vs. 16 series


> > {Original Message removed}

2002\12\06@105136 by Bob Ammerman

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> The hardware multiply isn't very helpful if you want to do more than 8bit
> multiplications, as it requires that you write everything the standard way
> instead of utilising the multiply function of the chip.

This is not true. You can use the hardware multiply for larger arguments.
Just imaging doing multiplication in base 256 and you'll see what I mean.

(hint: it will take 4 MUL instrucftions (plus some other instructions) to do
16 x 16 multiply. In general, for  A-bits x B-bits multiply, where A and B
are multiples of 8, you will need (A/8)*(B/8) MUL instructions.)

Bob Ammerman
RAm Systems

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2002\12\06@111041 by D. Jay Newman

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Sure it's helpful. For a 16 x 16 multiply, you treat the numbers as
if they were two-digit numbers in base 256. Aside from that it's
grade-school math.

   AB
 x CD
 ----
 EFGH

Yes, it's more complex than if there was a 16 x 16 multiply command, but
having the 8x8 potentially makes things faster than bitwise multiplication.

> The hardware multiply isn't very helpful if you want to do more than 8bit
> multiplications, as it requires that you write everything the standard way
> instead of utilising the multiply function of the chip.
>
> -Peter
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2002\12\06@120420 by Scott Dattalo

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On Fri, 6 Dec 2002, Bob Ammerman wrote:

> > The hardware multiply isn't very helpful if you want to do more than 8bit
> > multiplications, as it requires that you write everything the standard way
> > instead of utilising the multiply function of the chip.
>
> This is not true. You can use the hardware multiply for larger arguments.
> Just imaging doing multiplication in base 256 and you'll see what I mean.
>
> (hint: it will take 4 MUL instrucftions (plus some other instructions) to do
> 16 x 16 multiply. In general, for  A-bits x B-bits multiply, where A and B
> are multiples of 8, you will need (A/8)*(B/8) MUL instructions.)

(hint hint: it can actually be done with 3 MUL instrucftions (sic))

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2002\12\06@140148 by Wouter van Ooijen

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> > The 18 series has hardware multiply, table read from ROM (instead of
> requiring RETLW),
>
> Most (all ?) of the 16F parts can do this too.

Certainly not all can read (16F62x), I think even less can write
(16F7x?), and none can multiply.

Wouter van Ooijen

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2002\12\06@141223 by Harold Hallikainen

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    I NOW recall hearing something about that. THANKS for the reminder. Is rev A3 the current silicon? I've done maybe 20 boards with no problem at 40 MHz, though I don't want to depend on my limited sample size. To avoid a hardware and bill of materials change, I might just drop the clock multiplier in the configuration word and run it at 10 MHz. Again, is A3 the current revision? Are 40 MHz parts expected soon? How can I tell what silicon rev I have?

THANKS!

Harold


---------- Michael Rigby-Jones <RemoveMEmrjonesspam_OUTspamKILLspamBOOKHAM.COM> writes:

Are you aware that these parts are no longer rated to 40MHz?

http://www.microchip.com/download/lit/suppdoc/errata/80129b.pdf

Mike




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2002\12\06@151022 by Spehro Pefhany

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At 11:41 PM 12/6/02 +0800, you wrote:
>The hardware multiply isn't very helpful if you want to do more than 8bit
>multiplications, as it requires that you write everything the standard way
>instead of utilising the multiply function of the chip.

No. Use partial products and add. You can multiply an 'a' byte number times
a 'b' with (a * b)  8 x 8 multiplies.

Bes regards,

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2002\12\06@163640 by Olin Lathrop

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> The hardware multiply isn't very helpful if you want to do more than
8bit
> multiplications, as it requires that you write everything the standard
way
> instead of utilising the multiply function of the chip.

Huh?

You can build up a larger multiply using a number of 8 x 8 multiplies.
This may seem a little awkward, but it's still faster than a total
software shift and add loop.

Let's say A and B are two 16 bit numbers.  Each is made of two bytes,
A1:A0 and B1:B0.

 A = 256*A1 + A0
 B = 256*B1 + B0

 A * B =
 (256*A1 + A0) * (256*B1 + B0) =
 256*256*A1*B1 + 256*A1*B0 + 256*A0*B1 + A0*B0

This uses the hardware multiplier 4 times and you have to do a few
multi-byte additions, which are also easier on the 18 series due to the
add with carry instruction.  Obviously the multiplies by 256 and 256*256
are performed simply by shifting over one and two bytes.  All in all this
takes a lot fewer cycles than doing the same thing in a shift and add
software loop.


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2002\12\06@164050 by Olin Lathrop

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> (hint hint: it can actually be done with 3 MUL instrucftions (sic))

We are talking about a 16 x 16 into 32 bit multiply right?  If so, I don't
see how in the general case.  Care to elaborate?


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2002\12\07@062508 by Scott Dattalo

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On Fri, 6 Dec 2002, Olin Lathrop wrote:

> > (hint hint: it can actually be done with 3 MUL instrucftions (sic))
>
> We are talking about a 16 x 16 into 32 bit multiply right?  If so, I don't
> see how in the general case.  Care to elaborate?


P = (Ax + B) * (Cx +D)
 = ACx^2 + ADx + BCx + BD
 = ACx^2 + (A + B)(C + D)x - (AC + BD)x + BD

Only 3 multiplies, but a bunch of additions and overhead. 4 Multiplies is
much more efficient on a PIC 18F. On the 16's it may be a toss up.

Scott

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2002\12\07@090619 by Olin Lathrop

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> P = (Ax + B) * (Cx +D)
>   = ACx^2 + ADx + BCx + BD
>   = ACx^2 + (A + B)(C + D)x - (AC + BD)x + BD
>
> Only 3 multiplies, but a bunch of additions and overhead. 4 Multiplies
is
> much more efficient on a PIC 18F. On the 16's it may be a toss up.

Clever, I hadn't thought of that.  The three multiplies are A * C, B * D,
and (A+B) * (C+D).  It should be pointed out that the last of these is no
longer an 8 x 8 bit multiply, but rather a 9 x 9 bit.  As you said, this
would not be a suitable algorithm if the available hardware can do only an
8 x 8 multiply.


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2002\12\08@114026 by Scott Dattalo

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On Sat, 7 Dec 2002, Olin Lathrop wrote:

> > P = (Ax + B) * (Cx +D)
> >   = ACx^2 + ADx + BCx + BD
> >   = ACx^2 + (A + B)(C + D)x - (AC + BD)x + BD
> >
> > Only 3 multiplies, but a bunch of additions and overhead. 4 Multiplies
> is
> > much more efficient on a PIC 18F. On the 16's it may be a toss up.
>
> Clever, I hadn't thought of that.  The three multiplies are A * C, B * D,
> and (A+B) * (C+D).  It should be pointed out that the last of these is no
> longer an 8 x 8 bit multiply, but rather a 9 x 9 bit.  As you said, this
> would not be a suitable algorithm if the available hardware can do only an
> 8 x 8 multiply.

I learned this from Knuth, TAOCP Vol II. The "algorithm" above is the
first step of a general algorithm for multiplication. It's analogous to
FFT's for computing DFT's. Check out the section (in TAOCP) "How Fast can
we Multiply?", p. 294 in the 3rd edition. Knuth wrote the expansion in a
different (and more useful) form:

P = (Ax + B) * ( Cx + D)
  = ACx^2 + (A-B)(D-C)x + ACx + BDx + BD
  = AC*(x^2+x) + (A-B)(D-C)x + BD*(x+1)
  = ACx(x+1) + (A-B)(D-C)x + BD*(x+1)

The inner product is no longer n+1 bits, but it has changed from unsigned
to signed.

This algorithm can be applied recursively to arbitrarily large numbers. As
a result, according to Knuth, the classic multiplication algorithm is
reduced from order N^2 to order N^(log2(3)) ~ N^1.585. In our case, we
went from 4 to 3 multiplications, or 2^2 to 2^1.585 operations.

I've tried applying this algorithm at the bit level. Unfortunately, the
PIC assembly instructions are not as conducive as MIX (Knuth's
hypothetical computer).

Scott

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2002\12\09@105034 by Olin Lathrop

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>  P = (Ax + B) * ( Cx + D)
>    = ACx^2 + (A-B)(D-C)x + ACx + BDx + BD
>    = AC*(x^2+x) + (A-B)(D-C)x + BD*(x+1)
>    = ACx(x+1) + (A-B)(D-C)x + BD*(x+1)
>
> The inner product is no longer n+1 bits, but it has changed from
unsigned
> to signed.

I looks to me like it's N bits *plus* a sign bit.  If A and B are unsigned
bytes, they can range from 0 to 255.  A - B can therefore range from 255 -
0 = 255 to 0 - 255 = -255.  That requires a 9 bit signed value.


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