Post by thread:[PIC]: 16F876 EEPROM problem

Hi All, I'm currently working on (1 of about 5 projects) a design that saves the relevant settings to EE every time a button is presses. (Yes, I know a power fail detect would be a better solution) The problem is that when I write more than a few bytes in quick succession, the code locks up. I am disabling the global interrupt just before the "magic access" EE code and re-enabling afterwards then polling the WR bit so see when the EE if all done. Both the interrupts & main loop stop running when the fault occurs. By adding a 8ms delay to the write routine after the EE flags indicates complete, the problem goes away! So, it looks like the EE has not really finished writing despite what the WR flag says. I could change the code to use the EE interrupt-on-complete flag but I shouldn't need to - maybe I've missed something? Does anyone have a lot of experience with the 16F876's EEPROM? I've never had this with any of my F84 code. Regards... -- http://www.piclist.com hint: To leave the PICList spam_OUTpiclist-unsubscribe-requestTakeThisOuTmitvma.mit.edu

> The problem is that when I write more than a few bytes in quick > succession, the code locks up. I am disabling the global interrupt > just before the "magic access" EE code and re-enabling afterwards > then polling the WR bit so see when the EE if all done. Both the > interrupts & main loop stop running when the fault occurs. By adding > a 8ms delay to the write routine after the EE flags indicates complete, > the problem goes away! So, it looks like the EE has not really finished > writing despite what the WR flag says. I could change the code to use > the EE interrupt-on-complete flag but I shouldn't need to - maybe I've > missed something? Does anyone have a lot of experience with the > 16F876's EEPROM? I've never had this with any of my F84 code. I just checked my code, and it also waits on EECON1, WR to go low before starting another write. This code works fine in several applications writing tens of bytes at a time. Have you checked the bank settings to make sure you are really addressing EECON1? ***************************************************************** Olin Lathrop, embedded systems consultant in Devens Massachusetts (978) 772-3129, .....olinKILLspam@spam@embedinc.com, http://www.embedinc.com -- http://www.piclist.com hint: To leave the PICList piclist-unsubscribe-requestKILLspammitvma.mit.edu

> > The problem is that when I write more than a few bytes in quick > > succession, the code locks up. I am disabling the global interrupt > > just before the "magic access" EE code and re-enabling afterwards > > then polling the WR bit so see when the EE if all done. Both the > > interrupts & main loop stop running when the fault occurs. By adding > > a 8ms delay to the write routine after the EE flags indicates complete, > > the problem goes away! So, it looks like the EE has not really finished > > writing despite what the WR flag says. I could change the code to use > > the EE interrupt-on-complete flag but I shouldn't need to - maybe I've > > missed something? Does anyone have a lot of experience with the > > 16F876's EEPROM? I've never had this with any of my F84 code. Olin wrote: >I just checked my code, and it also waits on EECON1, WR to go low before >starting another write. This code works fine in several applications >writing tens of bytes at a time. Have you checked the bank settings to make >sure you are really addressing EECON1? Yes, bank is set correctly. Do you wait in the EE write routine or elsewhere? If in the write routine, is it before or after the actual write code? Regards... -- http://www.piclist.com hint: To leave the PICList .....piclist-unsubscribe-requestKILLspam.....mitvma.mit.edu

David Duffy wrote: > Yes, bank is set correctly. Do you wait in the EE write routine or elsewhere? > If in the write routine, is it before or after the actual write code? > Regards... I have been using the 16F876 for the PicPocket. Here is an excerpt from the code for internal eeprom writes. It's pretty much 'out of the book'. bsf STATUS,RP1 ; RAM Page 2 movlw ChipAdd movwf EEADR movlw 0x00 call EEwrite movlw 0xFF call EEwrite ... EEwrite bsf STATUS,RP1 ; RAM Page 2 movwf EEDATA bsf STATUS,RP0 ; RAM Page 3 bcf EECON1,EEPGD ; internal writes bsf EECON1,WREN movlw 55h movwf EECON2 movlw 0xAA movwf EECON2 bsf EECON1,WR WtEep btfsc EECON1,WR goto WtEep bcf EECON1,WREN bcf STATUS,RP0 ; RAM Page 2 incf EEADR clrf STATUS ; RAM page 0 return -- Best regards Tony mICro's http://www.picnpoke.com EraseMEsalesspam_OUTTakeThisOuTpicnpoke.com -- http://www.piclist.com hint: To leave the PICList piclist-unsubscribe-requestspam_OUTmitvma.mit.edu

At 10:21 AM 13/12/00 +1100, you wrote: {Quote hidden}>David Duffy wrote: > > > Yes, bank is set correctly. Do you wait in the EE write routine or > elsewhere? > > If in the write routine, is it before or after the actual write code? > > Regards... > >I have been using the 16F876 for the PicPocket. > >Here is an excerpt from the code for internal eeprom writes. > >It's pretty much 'out of the book'. > > > bsf STATUS,RP1 ; RAM Page 2 > movlw ChipAdd > movwf EEADR > movlw 0x00 > call EEwrite > movlw 0xFF > call EEwrite > ... > > >EEwrite bsf STATUS,RP1 ; RAM Page 2 > movwf EEDATA > > bsf STATUS,RP0 ; RAM Page 3 > bcf EECON1,EEPGD ; internal writes > bsf EECON1,WREN > movlw 55h > movwf EECON2 > movlw 0xAA > movwf EECON2 > bsf EECON1,WR > >WtEep btfsc EECON1,WR > goto WtEep > > bcf EECON1,WREN > bcf STATUS,RP0 ; RAM Page 2 > incf EEADR > clrf STATUS ; RAM page 0 > return Hi Tony, That's what I'm doing except I've got the interrupt to deal with. Are you using interrupts? If so, are you disabling them anywhere? Regards... -- http://www.piclist.com hint: To leave the PICList @spam@piclist-unsubscribe-requestKILLspammitvma.mit.edu

David Duffy wrote: > > Hi Tony, > That's what I'm doing except I've got the interrupt to deal with. > Are you using interrupts? If so, are you disabling them anywhere? > Regards... No, I'm not using interrupts. I guess you would have seen this, but this is where the data sheet puts the interrupt disable/enable code. bcf INTCON,GIE movlw 55h movwf EECON2 movlw 0xAA movwf EECON2 bsf EECON1,WR bsf INTCON,GIE I guess you then test the EEIF flag in your IRQ routine. -- Best regards Tony mICro's http://www.picnpoke.com KILLspamsalesKILLspampicnpoke.com -- http://www.piclist.com hint: To leave the PICList RemoveMEpiclist-unsubscribe-requestTakeThisOuTmitvma.mit.edu

Tony wrote: {Quote hidden}>David Duffy wrote: > > > > > Hi Tony, > > That's what I'm doing except I've got the interrupt to deal with. > > Are you using interrupts? If so, are you disabling them anywhere? > > Regards... > >No, I'm not using interrupts. > >I guess you would have seen this, but this is where the data sheet puts >the interrupt disable/enable code. > > bcf INTCON,GIE > movlw 55h > movwf EECON2 > movlw 0xAA > movwf EECON2 > bsf EECON1,WR > bsf INTCON,GIE Yes, that's what I'm doing in mine. >I guess you then test the EEIF flag in your IRQ routine. That's the next thing to try instead of using the WR flag. I will let the list know what happens. Regards... -- http://www.piclist.com hint: To leave the PICList spamBeGonepiclist-unsubscribe-requestspamBeGonemitvma.mit.edu

> Yes, bank is set correctly. Do you wait in the EE write routine or elsewhere? > If in the write routine, is it before or after the actual write code? > Regards... I do the wait before each write. The write routine returns as soon as it starts a write. This gives the processor a chance to do some other work while the write is going on. If the write finished before the next write call, then it never spends any time waiting. ***************************************************************** Olin Lathrop, embedded systems consultant in Devens Massachusetts (978) 772-3129, TakeThisOuTolinEraseMEspam_OUTembedinc.com, http://www.embedinc.com -- http://www.piclist.com hint: PICList Posts must start with ONE topic: [PIC]:,[SX]:,[AVR]: ->uP ONLY! [EE]:,[OT]: ->Other [BUY]:,[AD]: ->Ads

> >I guess you then test the EEIF flag in your IRQ routine. > > That's the next thing to try instead of using the WR flag. > I will let the list know what happens. > Regards... Just to let you know it works, I use interrupts and disable them around the critical section of the EEPROM write code. However, I don't enable the EEPROM interrupts. All the EEPROM write timing is done by making sure the WR bit is set properly before starting a write sequence. ***************************************************************** Olin Lathrop, embedded systems consultant in Devens Massachusetts (978) 772-3129, RemoveMEolinTakeThisOuTembedinc.com, http://www.embedinc.com -- http://www.piclist.com hint: PICList Posts must start with ONE topic: [PIC]:,[SX]:,[AVR]: ->uP ONLY! [EE]:,[OT]: ->Other [BUY]:,[AD]: ->Ads