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'[PIC]: 16F874 USART for DMX-512 - problems'
2002\02\21@142912 by Andrew Kilpatrick

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Hi,

I'm working on DMX-512 receiving code with the PIC16F874 using
the built in USART. DMX uses a break to start a new packet. It
is supposed to be 88uS (2 frame times @250Kbps), and the recommended
practice says that receivers should detect on slightly less, like
70uS.

So far I'm using the framing error flag to detect a break by
making sure that all the data bits are low. I've been getting a bit
of instability with this method. Is there a better way?

Also, the PIC16F874 datasheet is confusing when it talks about how
to read the error flag bits in the receiver. It says that the FERR
flag gets buffered in the FIFO, but the block diagram wouldn't suggest
that. Then it says to read the error flags before requesting a byte
from the FIFO. If FERR flags are buffered in the FIFO wouldn't this
mean that you'd be reading the wrong data unless you check the FERR
bit after you get data from the FIFO? Can someone please explain this?


Thanks,

Andrew

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2002\02\21@151740 by uter van ooijen & floortje hanneman

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> So far I'm using the framing error flag to detect a break by
> making sure that all the data bits are low. I've been getting a bit
> of instability with this method. Is there a better way?

I have absolutely no idea, but did you check http://www.qsl.net/n5tle/ ?
I helped someone to get the 16f876 receiver working and (once the hardware
was OK) it worked flawlessly.

Wouter van Ooijen

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2002\02\21@155940 by Harold M Hallikainen

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On Thu, 21 Feb 2002 14:17:17 -0500 Andrew Kilpatrick
<spam_OUTandrewTakeThisOuTspamANDREWKILPATRICK.ORG> writes:
{Quote hidden}

       I've done a fair amount of DMX transmission and reception using PICs
(mostly 16c74 and 18c452). I detect a break using the FE flag, then "eat
the byte" out of the usart data register, then go back to waiting for the
next incoming byte. After the FE, we assume the incoming byte will be the
start code byte (which should be zero). As each byte is brought in, FE is
checked. If an FE occurs, the state machine is reset to the point where
we are waiting for the start code byte. I don't check the contents of the
byte when there was an FE. I just throw it out. Seems to work (many
thousand units now out there).

Harold



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2002\02\21@160758 by Andrew Kilpatrick

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Hi Harold,

Thanks for the response. I'm still unclear as to when is the time to
check the error flags... before reading the byte from the data register
(if there is one) or after. I've seen code that does it both ways, but
the datasheet for the PIC suggests that you should read the error flags
first. Can you clear this up for me? Thanks.

Andrew

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2002\02\21@172310 by Harold M Hallikainen

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On Thu, 21 Feb 2002 16:06:43 -0500 Andrew Kilpatrick
<.....andrewKILLspamspam@spam@ANDREWKILPATRICK.ORG> writes:
> Hi Harold,
>
> Thanks for the response. I'm still unclear as to when is the time to
> check the error flags... before reading the byte from the data
> register
> (if there is one) or after. I've seen code that does it both ways,
> but
> the datasheet for the PIC suggests that you should read the error
> flags
> first. Can you clear this up for me? Thanks.
>

       I read them first, then read the data byte. If I had a framing error, I
reset the state machine and throw out the received byte.

Harold


FCC Rules Online at http://hallikainen.com/FccRules
Lighting control for theatre and television at http://www.dovesystems.com

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2002\02\21@180549 by Olin Lathrop

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> Also, the PIC16F874 datasheet is confusing when it talks about how
> to read the error flag bits in the receiver.

Don't blame this on the manual.  Actually it's quite clear.

> It says that the FERR
> flag gets buffered in the FIFO, but the block diagram wouldn't suggest
> that.

The block diagram is just that, not a schematic.

> Then it says to read the error flags before requesting a byte
> from the FIFO. If FERR flags are buffered in the FIFO wouldn't this
> mean that you'd be reading the wrong data unless you check the FERR
> bit after you get data from the FIFO? Can someone please explain this?

In section 10.2.2 "USART Asynchronous Receiver" on page 101 of DS3029C near
the bottom of the second colum of text it says "Reading RCREG will load bit
RX9D and FERR with new values, therefore, it is essential for the user to
read the RCSTA register *before* reading the RCREG register in order not to
lose the old FERR and RX9D information".  I don't think I can explain it any
better than that.


********************************************************************
Olin Lathrop, embedded systems consultant in Littleton Massachusetts
(978) 742-9014, olinspamKILLspamembedinc.com, http://www.embedinc.com

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2002\02\22@073139 by Edson Brusque

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Hello Harold,

>         I've done a fair amount of DMX transmission and reception using
PICs
> (mostly 16c74 and 18c452). I detect a break using the FE flag, then "eat
> the byte" out of the usart data register, then go back to waiting for the

   have you tried enabling 9 bit reception and using the RCSTA.RX9D bit to
check for a break? I'm actually doing this and it's workin ok.

   But I've been thinking lately that checking for the FE would be better
because the USART will be receiving only 8 bits and not 9 bits, so if the
device sending DMX is a bit fast and sends only 1 stop bit it will still
work.

   Best regards,

   Brusque

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2002\02\22@092613 by Olin Lathrop

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> Thanks for the response. I'm still unclear as to when is the time to
> check the error flags... before reading the byte from the data register
> (if there is one) or after. I've seen code that does it both ways, but
> the datasheet for the PIC suggests that you should read the error flags
> first. Can you clear this up for me? Thanks.

As the data sheet says, you read the FERR flag first.  Reading RCREG
advances the FIFO, which includes the FERR flag.  Therefore, FERR is always
**for the next byte to be read** from RCREG.


********************************************************************
Olin Lathrop, embedded systems consultant in Littleton Massachusetts
(978) 742-9014, .....olinKILLspamspam.....embedinc.com, http://www.embedinc.com

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2002\02\22@160138 by Harold M Hallikainen

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On Fri, 22 Feb 2002 09:29:54 -0300 Edson Brusque <EraseMEebrusquespam_OUTspamTakeThisOuTTERRA.COM.BR>
writes:
>
>     have you tried enabling 9 bit reception and using the RCSTA.RX9D
> bit to
> check for a break? I'm actually doing this and it's workin ok.
>
>     But I've been thinking lately that checking for the FE would be
> better
> because the USART will be receiving only 8 bits and not 9 bits, so
> if the
> device sending DMX is a bit fast and sends only 1 stop bit it will
> still
> work.
>

But the standard calls for 2 stop bits, doesn't it?

Harold

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Lighting control for theatre and television at http://www.dovesystems.com

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2002\02\23@092904 by Edson Brusque

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Hello Harold,

> But the standard calls for 2 stop bits, doesn't it?

   yes, you're right. But... who knows. Better be safe.

   Best regards,

   Brusque

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