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'[PIC]: port pin status in reset condition'
2002\10\03@150201 by Mike Mansheim

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Is the port pin status guaranteed to be something while the chip is in
the reset condition - specifically the internal reset during power up?
(16F87x or 18Fxxx)
I can't find this directly stated in the reference manual or the data
sheet.  I would have assumed that they would be tri-stated, but I'm not
sure.  I would base that assumption on the spec for the tris register
after a POR - they are all set as inputs.
However, the timing diagram that shows the "reset, watchdog timer,
oscillator start-up timer and power-up timer timing" is confusing me.
My apologies for being wordy - it is hard to describe this diagram in
text only without a lot of text.
During the "internal reset" period, caused by the power up and oscillator
timers, the i/o pins are shown as high or low.  The possibilities seem to
be that they are inputs and go where the circuit drives them, or they are
outputs with an indeterminate state.  There is a spec for the time to i/o
hi-impedance (I assume this = tri-stated) after MCLR low.  The diagram
shows the i/o pins at being halfway between high and low at this point.
However, once MCLR goes high again after the "reset pulse", the i/o pins
are shown as being high or low again, implying a change from the high-
impedance state.  Since this is how they are shown for the initial power
up reset, does this mean that they are NOT tri-stated during that time?
Thanks for any help.

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2002\10\03@154645 by =?iso-8859-1?Q?F=E1bio_Pereira?=

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Hi Mike,

When in reset, all I/O pins (except that ones used in the ICSP) are in the
high impedance state.

This information can be found on the programming specifications of the
devices, ex.: page 5 of DS39589A or page 5 of DS39576A.

Regards,

Fabio Pereira

{Original Message removed}

2002\10\03@161205 by Mike Mansheim

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Fabio Pereira:
> When in reset, all I/O pins (except that ones used in the ICSP) are in
> the high impedance state.

> This information can be found on the programming specifications of the
> devices, ex.: page 5 of DS39589A or page 5 of DS39576A.

Thanks for the reference.  According to those programming specs, the
"Programming/Verify mode" places the unused pins in the high impedance
state.  I'm concerned about the period of time during power-up when the
chip is held in reset - not during programming.  is it common knowledge
that the two modes are the same as far as the i/o pins are concerned?

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2002\10\03@201312 by =?iso-8859-1?Q?F=E1bio_Pereira?=

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Yes, the RESET is a previous state before entering the programming mode ...
Maybe it's not so clear, but when in reset, all I/O ports are placed in the
high impedance mode .

Regards,

Fabio Pereira

{Original Message removed}

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