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PICList Thread
'[PIC]: ISA peripheral'
2001\01\14@230244 by Donald L Burdette

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Hi all.

I want to put a PIC as a peripheral on the ISA bus, which is controlled
by a PC104 embedded computer running some version of DOS (don't know
whose, but probably not MS).  The PIC would be an IO device, mapped as
256 bytes of IO space.  The problem is that the PIC isn't fast enough to
watch the address select line (decoded externally), read the 8-bit
address, look up a data value, and put it on the data bus before the ISA
needs it.

I've thought about using a simple flip-flop to activate the /IOWAIT line,
but there's a limit as to how long you're allowed to hold that line.
It's two microseconds, and I don't think that's long enough.  Is there
any problem holding this line longer?  I think I would need less than 10
uS, maybe more like 4 or 5.

Has anyone had any experience in this area?  Any advice?  Good place to
look for working circuits?

Thanks in advance.


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2001\01\14@232355 by myke predko

Hi Donald,

Three comments:

1.  Have you looked at the "Parallel Slave Port" on the 40 Pin PICmicro
MCUs?  I have wired PICmicros to the ISA bus using this feature with just an
address decoder.

2.  For your application, you will have an issue because in this mode, you
will only be able to read/write to one address (not 256).  To access
multiple data bytes, you will have to come up with some kind of address/data
protocol.  This is a good thing because:

3.  The I/O space of the PC is very limited (for ISA, you should restrict
yourself to the address range 0x0100 to 0x03FF) - yes, the full I/O Space
address range is 64K, but only the first 1024 addresses are available for
peripherals and there isn't 256 contiguous addresses that can be used.
Using addresses above 0x0400 may result in conflicts with other devices
which should only be accessed by BIOS.


{Original Message removed}

2001\01\14@232616 by Antonio L Benci

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part 1 1730 bytes content-type:text/plain; charset=us-ascii (decoded 7bit)

I solved a similar problem by using FIFO memory. The FIFO memory
occupies one one io address. Write your data block to the FIFO then the
PIC can read the data block at its own pace. Status data can be either a
simple register or another FIFO for read back.

Donald L Burdette wrote:
{Quote hidden}

| Antonio (Nino) L. Benci                            |
| Professional Officer / Electronic Services Manager |
| School of Physics & Materials Engineering          |
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| M: 0414 924 833                                    |

part 2 596 bytes content-type:text/x-vcard; charset=us-ascii; name=Nino.Benci.vcf
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n:Benci;Antonio L
tel;cell:0414 924 833
tel;fax:+61 3 9905 3637
tel;home:0414 924 833
tel;work:+61 3 9905 3649
org:Monash University;School of Physics & Materials Engineering
title:Professional Officer/Electronic Services Manager
adr;quoted-printable:;;PO Box 27=0D=0ASchool of Physics and Materials Engineering=0D=0AMonash University;Monash University;VIC;3800;Australia
fn:Antonio L Benci

part 3 131 bytes
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2001\01\14@233018 by Bob Ammerman

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Actually, you can have a 256 address block on the ISA bus, but you have to
allocate it funny.

Instead of using the 8 lsbits to select among 256 addresses you use the top
6 and the bottom 2.

Bob Ammerman
RAm Systems
(contract development of high performance, high function, low-level

{Original Message removed}

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